ARM64: scalarize v1i64 mul operation

This is the second part of fixing PR19367. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205836 91177308-0d34-0410-b5e6-96231b3b80d8
tzlaine · Apr 9, 2014 · 87a7950 · 87a7950
1 parent 7db3c63
commit 87a7950
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diff --git a/lib/Target/ARM64/ARM64ISelLowering.cpp b/lib/Target/ARM64/ARM64ISelLowering.cpp
@@ -173,6 +173,8 @@ ARM64TargetLowering::ARM64TargetLowering(ARM64TargetMachine &TM)
   setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
   setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
 
+  setOperationAction(ISD::MUL, MVT::v1i64, Expand);
+
   // Custom lowering hooks are needed for XOR
   // to fold it into CSINC/CSINV.
   setOperationAction(ISD::XOR, MVT::i32, Custom);

diff --git a/test/CodeGen/ARM64/vmul.ll b/test/CodeGen/ARM64/vmul.ll
@@ -2027,3 +2027,10 @@ define <16 x i8> @test_pmull_high_64(<2 x i64> %l, <2 x i64> %r) nounwind {
 }
 
 declare <16 x i8> @llvm.arm64.neon.pmull64(i64, i64)
+
+define <1 x i64> @test_mul_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) nounwind {
+; CHECK-LABEL: test_mul_v1i64:
+; CHECK: mul
+  %prod = mul <1 x i64> %lhs, %rhs
+  ret <1 x i64> %prod
+}