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intel_adsp: ace20_lnl: Sort SoC nodes by address
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Sort SoC nodes by address to make it easier to find them.  As part
of this also move the intel-sha node under SoC where it belongs.

Signed-off-by: Kumar Gala <[email protected]>
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@galak @carlescufi
galak authored and carlescufi committed Apr 3, 2023
1 parent b8fb89d commit 5c76a81
Showing 1 changed file with 161 additions and 158 deletions.
319 changes: 161 additions & 158 deletions dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -116,60 +116,140 @@
#interrupt-cells = <3>;
};

adsp_host_ipc: ace_host_ipc@73000 {
compatible = "intel,adsp-host-ipc";
sspbase: ssp_base@28000 {
compatible = "intel,ssp-sspbase";
reg = <0x28000 0x1000>;
};

ssp0: ssp@28100 {
compatible = "intel,ssp-dai";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00028100 0x1000
0x00079C00 0x200>;
shim2 = <0x0D00 0x10>;
interrupts = <0x00 0 0>;
interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 1
&hda_link_in 1>;
dma-names = "tx", "rx";
power-domain = <&io0_domain>;
status = "okay";
reg = <0x73000 0x30>;
interrupts = <0 0 0>;
};

ssp1: ssp@29100 {
compatible = "intel,ssp-dai";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00029100 0x1000
0x00079C00 0x200>;
shim2 = <0x0D00 0x10>;
interrupts = <0x01 0 0>;
interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 2
&hda_link_in 2>;
dma-names = "tx", "rx";
power-domain = <&io0_domain>;
status = "okay";
};

adsp_idc: ace_idc@70400 {
compatible = "intel,adsp-idc";
reg = <0x70400 0x0400>;
interrupts = <24 0 0>;
ssp2: ssp@2a100 {
compatible = "intel,ssp-dai";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0002a100 0x1000
0x00079C00 0x200>;
shim2 = <0x0D00 0x10>;
interrupts = <0x02 0 0>;
interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 3
&hda_link_in 3>;
dma-names = "tx", "rx";
power-domain = <&io0_domain>;
status = "okay";
};

/* This is actually an array of per-core designware
* controllers, but the special setup and extra
* masking layer makes it easier for LNL to handle
* this internally.
*/
ace_intc: ace_intc@7ac00 {
compatible = "intel,ace-intc";
reg = <0x7ac00 0xc00>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <4 0 0>;
num-irqs = <28>;
interrupt-parent = <&core_intc>;
ssp3: ssp@2b100 {
compatible = "intel,ssp-dai";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0002b100 0x1000
0x00079C00 0x200>;
shim2 = <0x0D00 0x10>;
interrupts = <0x03 0 0>;
interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 4
&hda_link_in 4>;
dma-names = "tx", "rx";
power-domain = <&io0_domain>;
status = "okay";
};

ace_timestamp: ace_timestamp@72040 {
compatible = "intel,ace-timestamp";
reg = <0x72040 0x0032>;
ssp4: ssp@2c100 {
compatible = "intel,ssp-dai";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0002c100 0x1000
0x00079C00 0x200>;
shim2 = <0x0D00 0x10>;
interrupts = <0x04 0 0>;
interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 5
&hda_link_in 5>;
dma-names = "tx", "rx";
power-domain = <&io0_domain>;
status = "okay";
};

ace_art_counter: ace_art_counter@72058 {
compatible = "intel,ace-art-counter";
reg = <0x72058 0x0064>;
ssp5: ssp@2d100 {
compatible = "intel,ssp-dai";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0002d100 0x1000
0x00079C00 0x200>;
shim2 = <0x0D00 0x10>;
interrupts = <0x04 0 0>;
interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 6
&hda_link_in 6>;
dma-names = "tx", "rx";
power-domain = <&io0_domain>;
status = "okay";
};

ace_rtc_counter: ace_rtc_counter@72008 {
compatible = "intel,ace-rtc-counter";
reg = <0x72008 0x0064>;
mem_window0: mem_window@70200 {
compatible = "intel,adsp-mem-window";
reg = <0x70200 0x8>;
offset = <0x4000>;
memory = <&sram0>;
initialize;
read-only;
};

tts: tts@72000 {
compatible = "intel,adsp-tts";
reg = <0x72000 0x70>;
status = "okay";
mem_window1: mem_window@70208 {
compatible = "intel,adsp-mem-window";
reg = <0x70208 0x8>;
memory = <&sram0>;
};

timer: timer {
compatible = "intel,adsp-timer";
syscon = <&tts>;
mem_window2: mem_window@70210 {
compatible = "intel,adsp-mem-window";
reg = <0x70210 0x8>;
memory = <&sram0>;
};

mem_window3: mem_window@70218 {
compatible = "intel,adsp-mem-window";
reg = <0x70218 0x8>;
memory = <&sram0>;
read-only;
};

adsp_idc: ace_idc@70400 {
compatible = "intel,adsp-idc";
reg = <0x70400 0x0400>;
interrupts = <24 0 0>;
interrupt-parent = <&ace_intc>;
};

lps: lps@71ac0 {
Expand Down Expand Up @@ -223,43 +303,26 @@
};
};

sspbase: ssp_base@28000 {
compatible = "intel,ssp-sspbase";
reg = <0x28000 0x1000>;
tts: tts@72000 {
compatible = "intel,adsp-tts";
reg = <0x72000 0x70>;
status = "okay";
};

mem_window0: mem_window@70200 {
compatible = "intel,adsp-mem-window";
reg = <0x70200 0x8>;
offset = <0x4000>;
memory = <&sram0>;
initialize;
read-only;
};
mem_window1: mem_window@70208 {
compatible = "intel,adsp-mem-window";
reg = <0x70208 0x8>;
memory = <&sram0>;
ace_rtc_counter: ace_rtc_counter@72008 {
compatible = "intel,ace-rtc-counter";
reg = <0x72008 0x0064>;
};

mem_window2: mem_window@70210 {
compatible = "intel,adsp-mem-window";
reg = <0x70210 0x8>;
memory = <&sram0>;
};

mem_window3: mem_window@70218 {
compatible = "intel,adsp-mem-window";
reg = <0x70218 0x8>;
memory = <&sram0>;
read-only;
ace_timestamp: ace_timestamp@72040 {
compatible = "intel,ace-timestamp";
reg = <0x72040 0x0032>;
};
tlb: tlb@17e000 {
compatible = "intel,adsp-tlb";
reg = <0x17e000 0x1000>;
paddr-size = <12>;
exec-bit-idx = <14>;
write-bit-idx= <15>;

ace_art_counter: ace_art_counter@72058 {
compatible = "intel,ace-art-counter";
reg = <0x72058 0x0064>;
};

hda_host_out: dma@72800 {
Expand All @@ -280,6 +343,14 @@
status = "okay";
};

adsp_host_ipc: ace_host_ipc@73000 {
compatible = "intel,adsp-host-ipc";
status = "okay";
reg = <0x73000 0x30>;
interrupts = <0 0 0>;
interrupt-parent = <&ace_intc>;
};

hda_link_out: dma@79400 {
compatible = "intel,adsp-hda-link-out";
#dma-cells = <1>;
Expand All @@ -298,100 +369,32 @@
status = "okay";
};

ssp0:ssp@28100 {
compatible = "intel,ssp-dai";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00028100 0x1000
0x00079C00 0x200>;
shim2 = <0x0D00 0x10>;
interrupts = <0x00 0 0>;
interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 1
&hda_link_in 1>;
dma-names = "tx", "rx";
power-domain = <&io0_domain>;
status = "okay";
};

ssp1:ssp@29100 {
compatible = "intel,ssp-dai";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00029100 0x1000
0x00079C00 0x200>;
shim2 = <0x0D00 0x10>;
interrupts = <0x01 0 0>;
interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 2
&hda_link_in 2>;
dma-names = "tx", "rx";
power-domain = <&io0_domain>;
status = "okay";
};

ssp2:ssp@2a100 {
compatible = "intel,ssp-dai";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0002a100 0x1000
0x00079C00 0x200>;
shim2 = <0x0D00 0x10>;
interrupts = <0x02 0 0>;
interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 3
&hda_link_in 3>;
dma-names = "tx", "rx";
power-domain = <&io0_domain>;
status = "okay";
};

ssp3:ssp@2b100 {
compatible = "intel,ssp-dai";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0002b100 0x1000
0x00079C00 0x200>;
shim2 = <0x0D00 0x10>;
interrupts = <0x03 0 0>;
interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 4
&hda_link_in 4>;
dma-names = "tx", "rx";
power-domain = <&io0_domain>;
status = "okay";
/* This is actually an array of per-core designware
* controllers, but the special setup and extra
* masking layer makes it easier for LNL to handle
* this internally.
*/
ace_intc: ace_intc@7ac00 {
compatible = "intel,ace-intc";
reg = <0x7ac00 0xc00>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <4 0 0>;
num-irqs = <28>;
interrupt-parent = <&core_intc>;
};

ssp4:ssp@2c100 {
compatible = "intel,ssp-dai";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0002c100 0x1000
0x00079C00 0x200>;
shim2 = <0x0D00 0x10>;
interrupts = <0x04 0 0>;
interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 5
&hda_link_in 5>;
dma-names = "tx", "rx";
power-domain = <&io0_domain>;
status = "okay";
tlb: tlb@17e000 {
compatible = "intel,adsp-tlb";
reg = <0x17e000 0x1000>;
paddr-size = <12>;
exec-bit-idx = <14>;
write-bit-idx= <15>;
};

ssp5:ssp@2d100 {
compatible = "intel,ssp-dai";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0002d100 0x1000
0x00079C00 0x200>;
shim2 = <0x0D00 0x10>;
interrupts = <0x04 0 0>;
interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 6
&hda_link_in 6>;
dma-names = "tx", "rx";
power-domain = <&io0_domain>;
status = "okay";
timer: timer {
compatible = "intel,adsp-timer";
syscon = <&tts>;
};
};
};

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