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Pramod
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Nov 16, 2017
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,24 +1,57 @@ | ||
package uclid | ||
package lang | ||
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class ExternalTypeRewriterPass extends RewritePass { | ||
override def rewriteExternalType(extT : ExternalType, context : Scope) : Option[Type] = { | ||
println("external type: " + extT.toString) | ||
println("context::module: " + context.moduleDefinitionMap.toString) | ||
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context.moduleDefinitionMap.get(extT.moduleId) match { | ||
case Some(mod) => | ||
mod.typeDeclarationMap.get(extT.typeId) match { | ||
case Some(typ) => Some(typ) | ||
case None => | ||
println("Can't find type in module!") | ||
Some(extT) | ||
class ExternalTypeAnalysisPass extends ReadOnlyPass[(List[ModuleError], Map[ExternalType, Type])] { | ||
type T = (List[ModuleError], Map[ExternalType, Type]) | ||
override def applyOnExternalType(d : TraversalDirection.T, extT : ExternalType, in : T, context : Scope) : T = { | ||
if (d == TraversalDirection.Up) { | ||
if (in._2.contains(extT)) { | ||
in | ||
} else { | ||
context.moduleDefinitionMap.get(extT.moduleId) match { | ||
case Some(mod) => | ||
mod.typeDeclarationMap.get(extT.typeId) match { | ||
case Some(typ) => | ||
(in._1, in._2 + (extT -> typ)) | ||
case None => | ||
val msg = "Unknown type '%s' in module '%s'.".format(extT.typeId.toString, mod.id.toString) | ||
(ModuleError(msg, extT.typeId.position) :: in._1, in._2) | ||
} | ||
case None => | ||
val msg = "Unknown module: %s.".format(extT.moduleId.toString) | ||
(ModuleError(msg, extT.moduleId.position) :: in._1, in._2) | ||
} | ||
case None => | ||
println("Can't find module!") | ||
Some(extT) | ||
} | ||
} else { | ||
in | ||
} | ||
} | ||
} | ||
class ExternalTypeRewriter extends ASTRewriter( | ||
"ExternalTypeRewriter", new ExternalTypeRewriterPass()) | ||
class ExternalTypeAnalysis extends ASTAnalyzer("ExternalTypeAnalysis", new ExternalTypeAnalysisPass()) { | ||
in = Some((List.empty[ModuleError], Map.empty[ExternalType, Type])) | ||
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override def visit(module : Module, context : Scope) : Option[Module] = { | ||
val analysisResult = visitModule(module, _in.get, context) | ||
val errors = analysisResult._1 | ||
if (errors.size > 0) { | ||
throw new Utils.ParserErrorList(errors.map(e => (e.msg, e.position))) | ||
} | ||
_out = Some(analysisResult) | ||
return Some(module) | ||
} | ||
} | ||
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class ExternalTypeRewriterPass extends RewritePass { | ||
lazy val manager : PassManager = analysis.manager | ||
lazy val externalTypeAnalysis = manager.pass("ExternalTypeAnalysis").asInstanceOf[ExternalTypeAnalysis] | ||
lazy val typeMap : Map[ExternalType, Type] = externalTypeAnalysis.out.get._2 | ||
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override def rewriteExternalType(extT : ExternalType, context : Scope) : Option[Type] = { | ||
val typP = typeMap.get(extT) | ||
Utils.assert(typP.isDefined, "Unknown external types must have been eliminated by now.") | ||
typP | ||
} | ||
} | ||
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class ExternalTypeRewriter extends ASTRewriter("ExternalTypeRewriter", new ExternalTypeRewriterPass()) | ||
|
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,19 +1,74 @@ | ||
module common { | ||
type addr_t = bv8; | ||
type data_t = bv8; | ||
type opcode_t = enum { add, sub, load, store }; | ||
type mem_t = [addr_t]data_t; | ||
type word_t = bv8; | ||
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type op_t = enum { add, sub, load, store }; | ||
type mem_t = [addr_t]word_t; | ||
} | ||
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module main { | ||
module cpu { | ||
type addr_t = common :: addr_t; | ||
type mem_t = common :: mem_t; | ||
type word_t = common :: word_t; | ||
type op_t = common :: op_t; | ||
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type regindex_t; | ||
type regs_t = [regindex_t]word_t; | ||
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var mem : mem_t; | ||
var regs : regs_t; | ||
var pc : addr_t; | ||
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function word2op(w : word_t) : op_t; | ||
function word2reg0(w : word_t) : regindex_t; | ||
function word2reg1(w : word_t) : regindex_t; | ||
function word2nextPC(w : word_t) : addr_t; | ||
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procedure next_instruction() returns () { | ||
var inst : word_t; | ||
var op : op_t; | ||
var r0ind : regindex_t; | ||
var r1ind : regindex_t; | ||
var r0 : word_t; | ||
var r1 : word_t; | ||
var result : word_t; | ||
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// get the next instruction. | ||
inst := mem[pc]; | ||
// find its operation | ||
op := word2op(inst); | ||
// and its operands | ||
r0ind := word2reg0(inst); | ||
r1ind := word2reg1(inst); | ||
r0 := regs[r0ind]; | ||
r1 := regs[r1ind]; | ||
// now execute | ||
case | ||
(op == add) : { result := r0 + r1; } | ||
(op == sub) : { result := r0 - r1; } | ||
(op == load) : { result := mem[r1]; } | ||
(op == store) : { result := r0; mem[r0] := r1; } | ||
esac | ||
regs[r0ind] := result; | ||
} | ||
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init { | ||
assume (forall (r : regindex_t) :: regs[r] == 0bv8); | ||
} | ||
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next { | ||
call () := next_instruction(); | ||
} | ||
} | ||
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module main { | ||
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instance cpu_i : cpu(); | ||
next { | ||
call (cpu_i); | ||
} | ||
control { | ||
print_module; | ||
} | ||
} | ||
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