Merge branch 'p-android-omap-3.0' of git://git.omapzoom.org/kernel/om…

…ap into p-android-omap-3.0

drivers/misc/gcx/gccore/gcqueue.c

@@ -567,10 +567,13 @@ static int gccmdthread(void *_gccorecontext)
 		/* Wait for ready signal. If 'ready' is signaled before the
 		 * call times out, signaled is set to a value greater then
 		 * zero. If the call times out, signaled is set to zero. */
-		signaled = wait_for_completion_timeout(&gcqueue->ready,
-						       timeout);
+		signaled = wait_for_completion_interruptible_timeout(
+			&gcqueue->ready, timeout);
 		GCDBG(GCZONE_THREAD, "wait(ready) = %d.\n", signaled);
 
+		if (signaled < 0)
+			continue;
+
 		/* Get triggered interrupts. */
 		ints2process = triggered = atomic_read(&gcqueue->triggered);
 		GCDBG(GCZONE_THREAD, "int = 0x%08X.\n", triggered);
@@ -787,6 +790,7 @@ static int gccmdthread(void *_gccorecontext)
 				GCDBG(GCZONE_THREAD, "thread timedout.\n");
 
 			if (gcqueue->gcmoterminator == NULL) {
+				gcqueue->suspend = false;
 				GCUNLOCK(&gcqueue->queuelock);
 				continue;
 			}
@@ -811,21 +815,34 @@ static int gccmdthread(void *_gccorecontext)
 				continue;
 			}
 
-			GCDBG(GCZONE_THREAD,
-			      "execution finished, shutting down.\n");
-
 			/* Free the queue. */
 			while (!list_empty(&gcqueue->queue)) {
 				head = gcqueue->queue.next;
 				headcmdbuf = list_entry(head,
 							struct gccmdbuf,
 							link);
 
+				if (!list_empty(&headcmdbuf->events)) {
+					/* found events, there must be
+					 * pending interrupts */
+					break;
+				}
+
 				/* Free the entry. */
 				gcqueue_free_cmdbuf(gcqueue, headcmdbuf,
 						    NULL);
 			}
 
+			if (!list_empty(&gcqueue->queue)) {
+				GCDBG(GCZONE_THREAD,
+					"aborting shutdown to process events\n");
+				GCUNLOCK(&gcqueue->queuelock);
+				continue;
+			}
+
+			GCDBG(GCZONE_THREAD,
+			      "execution finished, shutting down.\n");
+
 			/* Convert WAIT to END. */
 			gcqueue->gcmoterminator->u2.end.cmd.raw
 				= gccmdend_const.cmd.raw;
@@ -839,6 +856,8 @@ static int gccmdthread(void *_gccorecontext)
 			/* Set idle state. */
 			complete(&gcqueue->stopped);
 
+			gcqueue->suspend = false;
+
 			/* Set timeout to infinity. */
 			timeout = MAX_SCHEDULE_TIMEOUT;
 
@@ -1611,8 +1630,7 @@ enum gcerror gcqueue_wait_idle(struct gccorecontext *gccorecontext)
 
 	/* Wait for GPU to stop. */
 	count = 0;
-	while (!completion_done(&gcqueue->stopped)) {
-		/* Not stopped, sleep. */
+	while (gcqueue->suspend) {
 		wait_for_completion_timeout(&gcqueue->sleep, timeout);
 
 		/* Waiting too long? */
@@ -1623,9 +1641,6 @@ enum gcerror gcqueue_wait_idle(struct gccorecontext *gccorecontext)
 		}
 	}
 
-	/* Reset suspend flag. */
-	gcqueue->suspend = false;
-
 	GCEXIT(GCZONE_THREAD);
 	return gcerror;
 }

drivers/power/twl6030_bci_battery.c

@@ -1622,7 +1622,9 @@ static int capacity_changed(struct twl6030_bci_device_info *di)
 	/* Setting the capacity level only makes sense when on
 	 * the battery is powering the board.
 	 */
-	if (di->charge_status == POWER_SUPPLY_STATUS_DISCHARGING) {
+	if ((di->charge_status == POWER_SUPPLY_STATUS_DISCHARGING) ||
+		(di->charge_status == POWER_SUPPLY_STATUS_NOT_CHARGING)) {
+
 		if (di->voltage_mV < 3500)
 			curr_capacity = 5;
 		else if (di->voltage_mV < 3600 && di->voltage_mV >= 3500)
@@ -1634,7 +1636,7 @@ static int capacity_changed(struct twl6030_bci_device_info *di)
 		else if (di->voltage_mV < 3900 && di->voltage_mV >= 3800)
 			curr_capacity = 90;
 		else if (di->voltage_mV >= 3900)
-				curr_capacity = 100;
+			curr_capacity = 100;
 	}
 
 	/* if we disabled charging to check capacity,

drivers/usb/host/ohci-hub.c

@@ -490,6 +490,9 @@ ohci_hub_status_data (struct usb_hcd *hcd, char *buf)
 	int		rhsc_status;
 	unsigned long	flags;
 
+	if (!HC_IS_RUNNING(hcd->state))
+		return 0;
+
 	spin_lock_irqsave (&ohci->lock, flags);
 	if (!HCD_HW_ACCESSIBLE(hcd))
 		goto done;

drivers/video/omap2/displays/panel-tc358765.c

@@ -768,6 +768,12 @@ static int tc358765_power_on(struct omap_dss_device *dssdev)
 	/* reset tc358765 bridge */
 	tc358765_hw_reset(dssdev);
 
+	/* We need to wait at least 100ms after power-on and before
+	 * turning on DDR clock. Otherwise display can be not initialithed
+	 * after resume, time to time. Delay in tc358765_hw_reset() function
+	 * also plays role. */
+	msleep(100);
+
 	/* do extra job to match kozio registers (???) */
 	dsi_videomode_panel_preinit(dssdev);
 

drivers/video/omap2/dss/manager.c

@@ -590,6 +590,7 @@ struct manager_cache_data {
 	bool cpr_enable;
 	struct omap_dss_cpr_coefs cpr_coefs;
 	bool skip_init;
+	bool m2m_only;
 };
 
 static struct {
@@ -1757,6 +1758,65 @@ static void dss_apply_irq_handler(void *data, u32 mask)
 	spin_unlock(&dss_cache.lock);
 }
 
+/* This function is needed for turning on/turning off DISPC clock for M2M mode
+ * with blanked panel. Essentially, this function increments/decrements counter
+ * of users of DISPC. */
+void dss_m2m_clock_handling(struct omap_overlay_manager *mgr)
+{
+	struct manager_cache_data *mc;
+	bool mc_m2m_only;
+
+	mc = &dss_cache.manager_cache[mgr->id];
+	mc_m2m_only = mc->m2m_only;
+
+	if (mgr->m2m_only && !mc_m2m_only)
+		dispc_runtime_get();
+	else if (!mgr->m2m_only && mc_m2m_only)
+		dispc_runtime_put();
+}
+
+static void dss_m2m_apply_handler(void)
+{
+	struct manager_cache_data *mc;
+	struct overlay_cache_data *oc;
+	const int num_ovls = dss_feat_get_num_ovls();
+	const int num_mgrs = dss_feat_get_num_mgrs();
+	int i;
+	bool mgr_busy[MAX_DSS_MANAGERS];
+
+	for (i = 0; i < MAX_DSS_MANAGERS; i++) {
+		if (i < num_mgrs) {
+			if (mgrs[i] && mgrs[i]->m2m_only)
+				mgr_busy[i] = false;
+			else
+				mgr_busy[i] = dispc_go_busy(i);
+		} else
+			mgr_busy[i] = false;
+	}
+
+	for (i = 0; i < num_ovls; ++i) {
+		oc = &dss_cache.overlay_cache[i];
+		if (!mgr_busy[oc->channel] && oc->shadow_dirty) {
+			dss_ovl_program_cb(&oc->cb, i);
+			oc->dispc_channel = oc->channel;
+			oc->shadow_dirty = false;
+		}
+	}
+
+	for (i = 0; i < num_mgrs; ++i) {
+		mc = &dss_cache.manager_cache[i];
+		if (!mgr_busy[i] && mc->shadow_dirty) {
+			if (mgrs[i] && mgrs[i]->device)
+				mgrs[i]->device->first_vsync = true;
+
+			dss_ovl_program_cb(&mc->cb, i);
+			mc->shadow_dirty = false;
+		}
+	}
+
+	configure_dispc();
+}
+
 static int omap_dss_mgr_blank(struct omap_overlay_manager *mgr,
 			bool wait_for_go)
 {
@@ -1816,21 +1876,29 @@ static int omap_dss_mgr_blank(struct omap_overlay_manager *mgr,
 	mgr->info.cb.fn = NULL;
 	mc->dirty = true;
 	mgr->info_dirty = false;
+	mc->m2m_only = mgr->m2m_only;
 
 	/*
 	 * TRICKY: Enable apply irq even if not waiting for vsync, so that
 	 * DISPC programming takes place in case GO bit was on.
 	 */
-	if (!dss_cache.irq_enabled) {
-		u32 mask;
+	if (mgr->m2m_only) {
+		configure_dispc();
+		dss_m2m_apply_handler();
+	} else {
+		if (!dss_cache.irq_enabled) {
+			u32 mask;
 
-		mask = DISPC_IRQ_VSYNC	| DISPC_IRQ_EVSYNC_ODD |
-			DISPC_IRQ_EVSYNC_EVEN;
-		if (dss_has_feature(FEAT_MGR_LCD2))
-			mask |= DISPC_IRQ_VSYNC2;
+			mask = DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_ODD |
+							DISPC_IRQ_EVSYNC_EVEN;
 
-		r = omap_dispc_register_isr(dss_apply_irq_handler, NULL, mask);
-		dss_cache.irq_enabled = true;
+			if (dss_has_feature(FEAT_MGR_LCD2))
+				mask |= DISPC_IRQ_VSYNC2;
+
+			r = omap_dispc_register_isr(dss_apply_irq_handler,
+								NULL, mask);
+			dss_cache.irq_enabled = true;
+		}
 	}
 
 	if (!r_get) {
@@ -2075,6 +2143,12 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
 
 	mc->skip_init = dssdev->skip_init;
 
+	/* WA: Do not set GO bit on manager */
+	if (mgr->m2m_only)
+		mc->skip_init = true;
+
+	mc->m2m_only = mgr->m2m_only;
+
 skip_mgr:
 
 	/* XXX TODO: Try to get fifomerge working. The problem is that it
@@ -2138,18 +2212,25 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
 	}
 
 	r = 0;
-	if (!dss_cache.irq_enabled) {
-		u32 mask;
+	if (mgr->m2m_only) {
+		configure_dispc();
+		dss_m2m_apply_handler();
+	} else {
+		if (!dss_cache.irq_enabled) {
+			u32 mask;
 
-		mask = DISPC_IRQ_VSYNC	| DISPC_IRQ_EVSYNC_ODD |
-			DISPC_IRQ_EVSYNC_EVEN;
-		if (dss_has_feature(FEAT_MGR_LCD2))
-			mask |= DISPC_IRQ_VSYNC2;
+			mask = DISPC_IRQ_VSYNC | DISPC_IRQ_EVSYNC_ODD |
+							DISPC_IRQ_EVSYNC_EVEN;
 
-		r = omap_dispc_register_isr(dss_apply_irq_handler, NULL, mask);
-		dss_cache.irq_enabled = true;
+			if (dss_has_feature(FEAT_MGR_LCD2))
+				mask |= DISPC_IRQ_VSYNC2;
+
+			r = omap_dispc_register_isr(dss_apply_irq_handler,
+								NULL, mask);
+			dss_cache.irq_enabled = true;
+		}
+		configure_dispc();
 	}
-	configure_dispc();
 
 done:
 	spin_unlock_irqrestore(&dss_cache.lock, flags);

drivers/video/omap2/dsscomp/dsscomp.h

@@ -113,7 +113,7 @@ struct dsscomp_data {
 	void (*extra_cb)(void *data, int status);
 	void *extra_cb_data;
 	bool must_apply;	/* whether composition must be applied */
-
+	bool m2m_only;
 #ifdef CONFIG_DEBUG_FS
 	struct list_head dbg_q;
 	u32 dbg_used;