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[AArch64] Generate zeroing forms of certain SVE2.2 instructions (11/1…
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…1) (llvm#116837)

SVE2.2 introduces instructions with predicated forms with zeroing of
the inactive lanes. This allows in some cases to save a `movprfx` or
a `mov` instruction when emitting code for `_x` or `_z` variants of
intrinsics.

This patch adds support for emitting the zeroing forms of certain
`SXTB`, `UXTB`, `SXTH`, `UXTH`, `SXTW`, and `UXTW` instructions.
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@momchil-velikov
momchil-velikov authored Jan 27, 2025
1 parent 754b946 commit 5d6d982
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12 changes: 6 additions & 6 deletions llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -4325,14 +4325,14 @@ let Predicates = [HasSVE2p2_or_SME2p2] in {
defm FNEG_ZPzZ : sve_int_un_pred_arit_bitwise_fp_z<0b101, "fneg", AArch64fneg_mt>;

// SVE2p2 integer unary arithmetic, zeroing predicate
defm SXTB_ZPzZ : sve_int_un_pred_arit_h_z<0b000, "sxtb">;
defm UXTB_ZPzZ : sve_int_un_pred_arit_h_z<0b001, "uxtb">;
defm SXTH_ZPzZ : sve_int_un_pred_arit_w_z<0b010, "sxth">;
defm UXTH_ZPzZ : sve_int_un_pred_arit_w_z<0b011, "uxth">;
defm SXTB_ZPzZ : sve_int_un_pred_arit_h_z<0b000, "sxtb", AArch64sxt_mt>;
defm UXTB_ZPzZ : sve_int_un_pred_arit_h_z<0b001, "uxtb", AArch64uxt_mt>;
defm SXTH_ZPzZ : sve_int_un_pred_arit_w_z<0b010, "sxth", AArch64sxt_mt>;
defm UXTH_ZPzZ : sve_int_un_pred_arit_w_z<0b011, "uxth", AArch64uxt_mt>;
defm ABS_ZPzZ : sve_int_un_pred_arit_z< 0b110, "abs", AArch64abs_mt>;
defm NEG_ZPzZ : sve_int_un_pred_arit_z< 0b111, "neg", AArch64neg_mt>;
def SXTW_ZPzZ_D : sve_int_un_pred_arit_z<0b11, 0b1000, "sxtw", ZPR64>;
def UXTW_ZPzZ_D : sve_int_un_pred_arit_z<0b11, 0b1010, "uxtw", ZPR64>;
defm SXTW_ZPzZ : sve_int_un_pred_arit_d_z<0b100, "sxtw", AArch64sxt_mt>;
defm UXTW_ZPzZ : sve_int_un_pred_arit_d_z<0b101, "uxtw", AArch64uxt_mt>;

// SVE predicate count
defm FIRSTP_XPP : sve_int_pcount_pred_tmp<0b001, "firstp">;
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28 changes: 26 additions & 2 deletions llvm/lib/Target/AArch64/SVEInstrFormats.td
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Original file line number Diff line number Diff line change
Expand Up @@ -662,6 +662,17 @@ multiclass SVE_InReg_Extend_PassthruUndef<ValueType vt, SDPatternOperator op, Va
(inst $PassThru, $Pg, $Src)>;
}

multiclass SVE_InReg_Extend_PassthruUndefZero<ValueType vt, SDPatternOperator op, ValueType pt,
ValueType inreg_vt, Instruction inst> {
let AddedComplexity = 1 in {
def : Pat<(vt (op pt:$Pg, vt:$Src, inreg_vt, (vt (SVEDup0Undef)))),
(inst $Pg, $Src)>;

def : Pat<(vt (op (pt (SVEAllActive:$Pg)), vt:$Src, inreg_vt, (vt (SVEAny)))),
(inst $Pg, $Src)>;
}
}

class SVE_Shift_DupImm_Pred_Pat<ValueType vt, SDPatternOperator op,
ValueType pt, ValueType it,
ComplexPattern cast, Instruction inst>
Expand Down Expand Up @@ -4930,10 +4941,14 @@ multiclass sve_int_un_pred_arit_h<bits<3> opc, string asm,
defm : SVE_InReg_Extend_PassthruUndef<nxv2i64, op, nxv2i1, nxv2i8, !cast<Pseudo>(NAME # _D_UNDEF)>;
}

multiclass sve_int_un_pred_arit_h_z<bits<3> opc, string asm> {
multiclass sve_int_un_pred_arit_h_z<bits<3> opc, string asm, SDPatternOperator op> {
def _H : sve_int_un_pred_arit_z<0b01, { opc, 0b0 }, asm, ZPR16>;
def _S : sve_int_un_pred_arit_z<0b10, { opc, 0b0 }, asm, ZPR32>;
def _D : sve_int_un_pred_arit_z<0b11, { opc, 0b0 }, asm, ZPR64>;

defm : SVE_InReg_Extend_PassthruUndefZero<nxv8i16, op, nxv8i1, nxv8i8, !cast<Instruction>(NAME # _H)>;
defm : SVE_InReg_Extend_PassthruUndefZero<nxv4i32, op, nxv4i1, nxv4i8, !cast<Instruction>(NAME # _S)>;
defm : SVE_InReg_Extend_PassthruUndefZero<nxv2i64, op, nxv2i1, nxv2i8, !cast<Instruction>(NAME # _D)>;
}

multiclass sve_int_un_pred_arit_w<bits<3> opc, string asm,
Expand All @@ -4953,9 +4968,12 @@ multiclass sve_int_un_pred_arit_w<bits<3> opc, string asm,
defm : SVE_InReg_Extend_PassthruUndef<nxv2i64, op, nxv2i1, nxv2i16, !cast<Pseudo>(NAME # _D_UNDEF)>;
}

multiclass sve_int_un_pred_arit_w_z<bits<3> opc, string asm> {
multiclass sve_int_un_pred_arit_w_z<bits<3> opc, string asm, SDPatternOperator op> {
def _S : sve_int_un_pred_arit_z<0b10, { opc, 0b0 }, asm, ZPR32>;
def _D : sve_int_un_pred_arit_z<0b11, { opc, 0b0 }, asm, ZPR64>;

defm : SVE_InReg_Extend_PassthruUndefZero<nxv4i32, op, nxv4i1, nxv4i16, !cast<Instruction>(NAME # _S)>;
defm : SVE_InReg_Extend_PassthruUndefZero<nxv2i64, op, nxv2i1, nxv2i16, !cast<Instruction>(NAME # _D)>;
}

multiclass sve_int_un_pred_arit_d<bits<3> opc, string asm,
Expand All @@ -4970,6 +4988,12 @@ multiclass sve_int_un_pred_arit_d<bits<3> opc, string asm,
defm : SVE_InReg_Extend_PassthruUndef<nxv2i64, op, nxv2i1, nxv2i32, !cast<Pseudo>(NAME # _D_UNDEF)>;
}

multiclass sve_int_un_pred_arit_d_z<bits<3> opc, string asm, SDPatternOperator op> {
def _D : sve_int_un_pred_arit_z<0b11, {opc, 0b0}, asm, ZPR64>;

defm : SVE_InReg_Extend_PassthruUndefZero<nxv2i64, op, nxv2i1, nxv2i32, !cast<Instruction>(NAME # _D)>;
}

multiclass sve_int_un_pred_arit_bitwise<bits<3> opc, string asm,
SDPatternOperator op> {
def _B : sve_int_un_pred_arit<0b00, { opc, 0b1 }, asm, ZPR8>,
Expand Down
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