z80: Updating and fixing the host test program and memory addressing

ve7it · Sep 12, 2014 · 74a59a1 · 74a59a1
1 parent d3f7f31
commit 74a59a1
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Showing 6 changed files with 87 additions and 85 deletions.
diff --git a/host/toplevel/host.debug.sv b/host/toplevel/host.debug.sv
@@ -107,9 +107,11 @@ uart_io uart_io_( .*, .reset(reset_stable), .Address(A[15:8]), .Data(D[7:0]), .I
 wire [7:0] RamData;
 wire we;
 
-assign D[7:0] = (A[15:8]=='0 && nMREQ==1 && nRD==1 && nWR==0) ? RamData  : {8{1'bz}};
-assign we = A[15:8]=='0 && nMREQ==1 && nRD==0 && nWR==1;
+// 1K is addressable with bits [9:0]
+// 1K *blocks* are selectable with bits [15:10]
+assign D[7:0] = (A[15:10]=='0 && nMREQ==1 && nRD==1 && nWR==0) ? RamData  : {8{1'bz}};
+assign we = A[15:10]=='0 && nMREQ==1 && nRD==0 && nWR==1;
 
-ram ram_( .address (A[9:0]), .clock (clk), .data (D[7:0]), .wren (we), .q (RamData[7:0]) );
+ram ram_( .address(A[9:0]), .clock(clk), .data(D[7:0]), .wren(we), .q(RamData[7:0]) );
 
 endmodule
diff --git a/host/toplevel/host.sv b/host/toplevel/host.sv
@@ -47,9 +47,11 @@ uart_io uart_io_( .*, .reset(!reset), .Address(A[15:8]), .Data(D[7:0]), .IORQ(nI
 wire [7:0] RamData;
 wire we;
 
-assign D[7:0] = (A[15:8]=='0 && nMREQ==1 && nRD==1 && nWR==0) ? RamData  : {8{1'bz}};
-assign we = A[15:8]=='0 && nMREQ==1 && nRD==0 && nWR==1;
+// 1K is addressable with bits [9:0]
+// 1K *blocks* are selectable with bits [15:10]
+assign D[7:0] = (A[15:10]=='0 && nMREQ==1 && nRD==1 && nWR==0) ? RamData  : {8{1'bz}};
+assign we = A[15:10]=='0 && nMREQ==1 && nRD==0 && nWR==1;
 
-ram ram_( .address (A[9:0]), .clock (clk), .data (D[7:0]), .wren (we), .q (RamData[7:0]) );
+ram ram_( .address(A[9:0]), .clock(clk), .data(D[7:0]), .wren(we), .q(RamData[7:0]) );
 
 endmodule