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Update dma sdk with new macro definitions to handle different DMA par…
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…ameters (esl-epfl#563)

Co-authored-by: Juan Sapriza <[email protected]>
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@LuigiGiuffrida98 @JuanSapriza
LuigiGiuffrida98 and JuanSapriza authored Aug 7, 2024
1 parent 19dcdb5 commit 98c47f9
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Showing 8 changed files with 270 additions and 1,056 deletions.
69 changes: 39 additions & 30 deletions hw/ip/dma/rtl/dma.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -52,7 +52,8 @@ module dma #(
logic [ 31:0] write_ptr_reg;
logic [ 31:0] write_address;
logic [ 31:0] dma_addr_cnt;
logic [ 2:0] dma_cnt_du;
logic [ 2:0] dma_src_cnt_du;
logic [ 2:0] dma_dst_cnt_du;
logic dma_start;
logic dma_done;
logic dma_window_event;
Expand Down Expand Up @@ -297,57 +298,57 @@ module dma #(
};
assign idle_to_right_ex = {
|reg2hw.pad_top.q == 1'b0 && |reg2hw.pad_left.q == 1'b0 && |reg2hw.pad_right.q == 1'b1
&& dma_src_cnt_d1 == ({11'h0, reg2hw.pad_right.q} + {14'h0, dma_cnt_du})
&& dma_src_cnt_d1 == ({11'h0, reg2hw.pad_right.q} + {14'h0, dma_dst_cnt_du})
};
assign idle_to_bottom_ex = {
|reg2hw.pad_top.q == 1'b0 && |reg2hw.pad_left.q == 1'b0 && |reg2hw.pad_right.q == 1'b0 && |reg2hw.pad_bottom.q == 1'b1
&& dma_src_cnt_d2 == ({11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_cnt_du}) && dma_src_cnt_d1 == ({14'h0, dma_cnt_du})
&& dma_src_cnt_d2 == ({11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_dst_cnt_du}) && dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du})
};
assign top_ex_to_top_dn = {
dma_src_cnt_d2 == ({1'h0, reg2hw.size_d2.q} + {11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_cnt_du}) && dma_src_cnt_d1 == ({14'h0, dma_cnt_du}) && |reg2hw.pad_left.q == 1'b0
dma_src_cnt_d2 == ({1'h0, reg2hw.size_d2.q} + {11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_dst_cnt_du}) && dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du}) && |reg2hw.pad_left.q == 1'b0
};
assign top_ex_to_left_ex = {
dma_src_cnt_d2 == ({1'h0, reg2hw.size_d2.q} + {11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_cnt_du}) && dma_src_cnt_d1 == ({14'h0, dma_cnt_du}) && |reg2hw.pad_left.q == 1'b1
dma_src_cnt_d2 == ({1'h0, reg2hw.size_d2.q} + {11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_dst_cnt_du}) && dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du}) && |reg2hw.pad_left.q == 1'b1
};
assign top_dn_to_right_ex = {
|reg2hw.pad_left.q == 1'b0 && |reg2hw.pad_right.q == 1'b1 && dma_src_cnt_d1 == ({11'h0, reg2hw.pad_right.q} + {14'h0, dma_cnt_du})
|reg2hw.pad_left.q == 1'b0 && |reg2hw.pad_right.q == 1'b1 && dma_src_cnt_d1 == ({11'h0, reg2hw.pad_right.q} + {14'h0, dma_dst_cnt_du})
};
assign top_dn_to_bottom_ex = {
|reg2hw.pad_left.q == 1'b0 && |reg2hw.pad_right.q == 1'b0 && |reg2hw.pad_bottom.q == 1'b1 && dma_src_cnt_d2 == ({11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_cnt_du}) && dma_src_cnt_d1 == ({14'h0, dma_cnt_du})
|reg2hw.pad_left.q == 1'b0 && |reg2hw.pad_right.q == 1'b0 && |reg2hw.pad_bottom.q == 1'b1 && dma_src_cnt_d2 == ({11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_dst_cnt_du}) && dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du})
};
assign top_dn_to_idle = {
|reg2hw.pad_left.q == 1'b0 && |reg2hw.pad_right.q == 1'b0 && |reg2hw.pad_bottom.q == 1'b0 && |dma_src_cnt_d2 == 1'b0
};
assign left_ex_to_left_dn = {
dma_src_cnt_d1 == ({1'h0, reg2hw.size_d1.q} + {11'h0, reg2hw.pad_right.q} + {14'h0, dma_cnt_du})
dma_src_cnt_d1 == ({1'h0, reg2hw.size_d1.q} + {11'h0, reg2hw.pad_right.q} + {14'h0, dma_dst_cnt_du})
};
assign left_dn_to_left_ex = {
dma_src_cnt_d1 == ({14'h0, dma_cnt_du}) && dma_src_cnt_d2 != ({14'h0, dma_cnt_du} + {11'h0, reg2hw.pad_bottom.q}) && |reg2hw.pad_right.q == 1'b0
dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du}) && dma_src_cnt_d2 != ({14'h0, dma_dst_cnt_du} + {11'h0, reg2hw.pad_bottom.q}) && |reg2hw.pad_right.q == 1'b0
};
assign left_dn_to_right_ex = {
|reg2hw.pad_right.q == 1'b1 && dma_src_cnt_d1 == ({11'h0, reg2hw.pad_right.q} + {14'h0, dma_cnt_du})
|reg2hw.pad_right.q == 1'b1 && dma_src_cnt_d1 == ({11'h0, reg2hw.pad_right.q} + {14'h0, dma_dst_cnt_du})
};
assign left_dn_to_bottom_ex = {
|reg2hw.pad_right.q == 1'b0 && |reg2hw.pad_bottom.q == 1'b1 && dma_src_cnt_d2 == ({11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_cnt_du}) && dma_src_cnt_d1 == ({14'h0, dma_cnt_du})
|reg2hw.pad_right.q == 1'b0 && |reg2hw.pad_bottom.q == 1'b1 && dma_src_cnt_d2 == ({11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_dst_cnt_du}) && dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du})
};
assign left_dn_to_idle = {
|reg2hw.pad_right.q == 1'b0 && |reg2hw.pad_bottom.q == 1'b0 && |dma_src_cnt_d2 == 1'b0
};
assign right_ex_to_right_dn = {
dma_src_cnt_d1 == ({14'h0, dma_cnt_du}) && dma_src_cnt_d2 != ({11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_cnt_du}) && |reg2hw.pad_left.q == 1'b0
dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du}) && dma_src_cnt_d2 != ({11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_dst_cnt_du}) && |reg2hw.pad_left.q == 1'b0
};
assign right_ex_to_left_ex = {
dma_src_cnt_d1 == ({14'h0, dma_cnt_du}) && dma_src_cnt_d2 != ({11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_cnt_du}) && |reg2hw.pad_left.q == 1'b1
dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du}) && dma_src_cnt_d2 != ({11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_dst_cnt_du}) && |reg2hw.pad_left.q == 1'b1
};
assign right_ex_to_bottom_ex = {
|reg2hw.pad_bottom.q == 1'b1 && dma_src_cnt_d2 == ({11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_cnt_du}) && dma_src_cnt_d1 == ({14'h0, dma_cnt_du})
|reg2hw.pad_bottom.q == 1'b1 && dma_src_cnt_d2 == ({11'h0, reg2hw.pad_bottom.q} + {14'h0, dma_dst_cnt_du}) && dma_src_cnt_d1 == ({14'h0, dma_dst_cnt_du})
};
assign right_dn_to_right_ex = {
dma_src_cnt_d1 == ({11'h0, reg2hw.pad_right.q} + {14'h0, dma_cnt_du}) && |reg2hw.pad_left.q == 1'b0
dma_src_cnt_d1 == ({11'h0, reg2hw.pad_right.q} + {14'h0, dma_dst_cnt_du}) && |reg2hw.pad_left.q == 1'b0
};
assign right_dn_to_idle = {|reg2hw.pad_bottom.q == 1'b0 && |dma_src_cnt_d2 == 1'b0};
assign bottom_ex_to_idle = {
dma_src_cnt_d1 == {14'h0, dma_cnt_du} && dma_src_cnt_d2 == {14'h0, dma_cnt_du}
dma_src_cnt_d1 == {14'h0, dma_dst_cnt_du} && dma_src_cnt_d2 == {14'h0, dma_dst_cnt_du}
};

assign write_address = address_mode ? fifo_addr_output : write_ptr_reg;
Expand Down Expand Up @@ -426,14 +427,14 @@ module dma #(
read_ptr_reg <= read_ptr_reg + {26'h0, dma_src_d1_inc};
end else if (dma_conf_2d == 1'b1 && pad_cnt_on == 1'b0) begin
if (read_ptr_update_sel == 1'b0) begin
if (dma_src_cnt_d1 == {14'h0, dma_cnt_du} && |dma_src_cnt_d2 == 1'b1) begin
if (dma_src_cnt_d1 == {14'h0, dma_src_cnt_du} && |dma_src_cnt_d2 == 1'b1) begin
/* In this case, the d1 is almost finished, so we need to increment the pointer by sizeof(d1)*data_unit */
read_ptr_reg <= read_ptr_reg + {9'h0, dma_src_d2_inc};
end else begin
read_ptr_reg <= read_ptr_reg + {26'h0, dma_src_d1_inc}; /* Increment of the d1 increment (stride) */
end
end else begin
if (dma_src_cnt_d1 == {14'h0, dma_cnt_du} && |dma_src_cnt_d2 == 1'b1) begin
if (dma_src_cnt_d1 == {14'h0, dma_src_cnt_du} && |dma_src_cnt_d2 == 1'b1) begin
/* In this case, the d1 is almost finished, so we need to increment the pointer by sizeof(d2)*data_unit */
read_ptr_reg <= src_ptr_reg;
end else begin
Expand All @@ -457,7 +458,7 @@ module dma #(
if (dma_start == 1'b1) begin
src_ptr_reg <= reg2hw.src_ptr.q + {26'h0, dma_src_d1_inc};
end else if (data_in_gnt == 1'b1 && dma_conf_2d == 1'b1 && pad_cnt_on == 1'b0 && read_ptr_update_sel == 1'b1 &&
(dma_src_cnt_d1 == {14'h0, dma_cnt_du} && |dma_src_cnt_d2 == 1'b1)) begin
(dma_src_cnt_d1 == {14'h0, dma_src_cnt_du} && |dma_src_cnt_d2 == 1'b1)) begin
src_ptr_reg <= src_ptr_reg + {26'h0, dma_src_d1_inc};
end
end
Expand Down Expand Up @@ -502,7 +503,7 @@ module dma #(
if (dma_conf_1d == 1'b1) begin
write_ptr_reg <= write_ptr_reg + {26'h0, dma_dst_d1_inc};
end else if (dma_conf_2d == 1'b1) begin
if (dma_dst_cnt_d1 == {14'h0, dma_cnt_du}) begin
if (dma_dst_cnt_d1 == {14'h0, dma_dst_cnt_du}) begin
// In this case, the d1 is finished, so we need to increment the pointer by sizeof(d1)*data_unit*strides
write_ptr_reg <= write_ptr_reg + {9'h0, dma_dst_d2_inc};
end else begin
Expand All @@ -526,16 +527,16 @@ module dma #(
end else if (data_in_gnt == 1'b1) begin
if (dma_conf_1d == 1'b1) begin
// 1D case
dma_src_cnt_d1 <= dma_src_cnt_d1 - {14'h0, dma_cnt_du};
dma_src_cnt_d1 <= dma_src_cnt_d1 - {14'h0, dma_src_cnt_du};
end else if (dma_conf_2d == 1'b1) begin
// 2D case
if (dma_src_cnt_d1 == {14'h0, dma_cnt_du}) begin
if (dma_src_cnt_d1 == {14'h0, dma_src_cnt_du}) begin
// In this case, the d1 is finished, so we need to decrement the d2 size and reset the d2 size
dma_src_cnt_d2 <= dma_src_cnt_d2 - {14'h0, dma_cnt_du};
dma_src_cnt_d2 <= dma_src_cnt_d2 - {14'h0, dma_src_cnt_du};
dma_src_cnt_d1 <= {1'h0, reg2hw.size_d1.q} + {11'h0, reg2hw.pad_left.q} + {11'h0, reg2hw.pad_right.q};
end else begin
// In this case, the d1 isn't finished, so we need to decrement the d1 size
dma_src_cnt_d1 <= dma_src_cnt_d1 - {14'h0, dma_cnt_du};
dma_src_cnt_d1 <= dma_src_cnt_d1 - {14'h0, dma_src_cnt_du};
end
end
end
Expand All @@ -556,15 +557,15 @@ module dma #(
end else if (data_out_gnt == 1'b1) begin
if (dma_conf_1d == 1'b1) begin
// 1D case
dma_dst_cnt_d1 <= dma_dst_cnt_d1 - {14'h0, dma_cnt_du};
dma_dst_cnt_d1 <= dma_dst_cnt_d1 - {14'h0, dma_dst_cnt_du};
end else if (dma_conf_2d == 1'b1) begin
// 2D case
if (dma_dst_cnt_d1 == {14'h0, dma_cnt_du}) begin
if (dma_dst_cnt_d1 == {14'h0, dma_dst_cnt_du}) begin
// In this case, the d1 is finished, so we need to reset the d2 size
dma_dst_cnt_d1 <= {1'h0, reg2hw.size_d1.q} + {11'h0, reg2hw.pad_left.q} + {11'h0, reg2hw.pad_right.q};
end else begin
// In this case, the d1 isn't finished, so we need to decrement the d1 size
dma_dst_cnt_d1 <= dma_dst_cnt_d1 - {14'h0, dma_cnt_du};
dma_dst_cnt_d1 <= dma_dst_cnt_d1 - {14'h0, dma_dst_cnt_du};
end
end
end
Expand All @@ -586,9 +587,17 @@ module dma #(

always_comb begin
case (dst_data_type)
DMA_DATA_TYPE_WORD: dma_cnt_du = 3'h4;
DMA_DATA_TYPE_HALF_WORD: dma_cnt_du = 3'h2;
DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_BYTE_: dma_cnt_du = 3'h1;
DMA_DATA_TYPE_WORD: dma_dst_cnt_du = 3'h4;
DMA_DATA_TYPE_HALF_WORD: dma_dst_cnt_du = 3'h2;
DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_BYTE_: dma_dst_cnt_du = 3'h1;
endcase
end

always_comb begin
case (src_data_type)
DMA_DATA_TYPE_WORD: dma_src_cnt_du = 3'h4;
DMA_DATA_TYPE_HALF_WORD: dma_src_cnt_du = 3'h2;
DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_BYTE_: dma_src_cnt_du = 3'h1;
endcase
end

Expand Down
26 changes: 0 additions & 26 deletions sw/applications/example_dma_2d/main.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -122,32 +122,6 @@ uint8_t stride_1d_cnt = 0;
uint8_t stride_2d_cnt = 0;
char passed = 1;

#ifdef TEST_ID_3

/* Function used to simplify register operations */
static inline volatile void write_register( uint32_t p_val,
uint32_t p_offset,
uint32_t p_mask,
uint8_t p_sel,
dma* peri )
{
/*
* The index is computed to avoid needing to access the structure
* as a structure.
*/
uint8_t index = p_offset / sizeof(int);

/*
* An intermediate variable "value" is used to prevent writing twice into
* the register.
*/
uint32_t value = (( uint32_t * ) peri ) [ index ];
value &= ~( p_mask << p_sel );
value |= (p_val & p_mask) << p_sel;
(( uint32_t * ) peri ) [ index ] = value;
};
#endif

int main()
{
#ifdef TEST_ID_0
Expand Down
23 changes: 0 additions & 23 deletions sw/applications/example_dma_multichannel/main.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -210,29 +210,6 @@ uint8_t window_flag[DMA_CH_NUM];
char passed = 1;
char flag = 0;

/* Function used to simplify the register operations */
static inline volatile void write_register( uint32_t p_val,
uint32_t p_offset,
uint32_t p_mask,
uint8_t p_sel,
dma* peri_chx )
{
/*
* The index is computed to avoid needing to access the structure
* as a structure.
*/
uint8_t index = p_offset / sizeof(int);

/*
* An intermediate variable "value" is used to prevent writing twice into
* the register.
*/
uint32_t value = (( uint32_t * ) peri_chx ) [ index ];
value &= ~( p_mask << p_sel );
value |= (p_val & p_mask) << p_sel;
(( uint32_t * ) peri_chx ) [ index ] = value;
};

/* Strong transaction ISR implementation */
void dma_intr_handler_trans_done(uint8_t channel)
{
Expand Down
76 changes: 53 additions & 23 deletions sw/applications/example_dma_sdk/main.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,29 +11,35 @@
// are performed correctly.

#include <stdint.h>
#include <stdio.h> // For compatibility with OH Group compiler
#include <stdlib.h>
#include "dma_sdk.h"
#include "dma.h" // For compatibility with OH Group compiler
#include "core_v_mini_mcu.h"
#include "x-heep.h"
#include "csr.h" // For compatibility with OH Group compiler

/* By default, printfs are activated for FPGA and disabled for simulation. */
#define PRINTF_IN_FPGA 1
#define PRINTF_IN_SIM 0
#define PRINTF_IN_FPGA 1
#define PRINTF_IN_SIM 0

#if TARGET_SIM && PRINTF_IN_SIM
#define PRINTF(fmt, ...) printf(fmt, ## __VA_ARGS__)
#define PRINTF(fmt, ...) printf(fmt, ##__VA_ARGS__)
#elif PRINTF_IN_FPGA && !TARGET_SIM
#define PRINTF(fmt, ...) printf(fmt, ## __VA_ARGS__)
#define PRINTF(fmt, ...) printf(fmt, ##__VA_ARGS__)
#else
#define PRINTF(...)
#define PRINTF(...)
#endif

#define SOURCE_BUFFER_SIZE_32b 5
#define SOURCE_BUFFER_SIZE_16b 5
#define SOURCE_BUFFER_SIZE_8b 5
#define CONST_VALUE_32B 123
#define CONST_VALUE_16B 123
#define CONST_VALUE_8B 123
#define SOURCE_BUFFER_SIZE_32b 5
#define SOURCE_BUFFER_SIZE_16b 5
#define SOURCE_BUFFER_SIZE_8b 5
#define CONST_VALUE_32B 123
#define CONST_NEG_VALUE_32B -123
#define CONST_VALUE_16B 123
#define CONST_NEG_VALUE_16B -123
#define CONST_VALUE_8B 123
#define CONST_NEG_VALUE_8B -123

static uint32_t source_32b[SOURCE_BUFFER_SIZE_32b];
static uint32_t destin_32b[SOURCE_BUFFER_SIZE_32b];
Expand All @@ -44,39 +50,63 @@ static uint16_t source_16b[SOURCE_BUFFER_SIZE_16b];
static uint8_t destin_8b[SOURCE_BUFFER_SIZE_8b];
static uint8_t source_8b[SOURCE_BUFFER_SIZE_8b];

static int32_t neg_source_32b[SOURCE_BUFFER_SIZE_32b];
static int32_t neg_destin_32b[SOURCE_BUFFER_SIZE_32b];

static int16_t neg_destin_16b[SOURCE_BUFFER_SIZE_16b];
static int16_t neg_source_16b[SOURCE_BUFFER_SIZE_16b];

static int8_t neg_destin_8b[SOURCE_BUFFER_SIZE_8b];
static int8_t neg_source_8b[SOURCE_BUFFER_SIZE_8b];

static uint32_t value_32b = CONST_VALUE_32B;
static uint16_t value_16b = CONST_VALUE_16B;
static uint8_t value_8b = CONST_VALUE_8B;

static int32_t neg_value_32b = CONST_NEG_VALUE_32B;
static int16_t neg_value_16b = CONST_NEG_VALUE_16B;
static int8_t neg_value_8b = CONST_NEG_VALUE_8B;

uint32_t i;
uint32_t errors = 0;

int main(){

int main()
{
dma_sdk_init();

dma_fill_32b( &source_32b, &value_32b, SOURCE_BUFFER_SIZE_32b, 0);
dma_copy_32b( &destin_32b, &source_32b, SOURCE_BUFFER_SIZE_32b, 0);
dma_fill((uint32_t)source_32b, (uint32_t)&value_32b, SOURCE_BUFFER_SIZE_32b, 0, DMA_DATA_TYPE_WORD, DMA_DATA_TYPE_WORD, 0);
dma_copy((uint32_t)destin_32b, (uint32_t)source_32b, SOURCE_BUFFER_SIZE_32b, 0, DMA_DATA_TYPE_WORD, DMA_DATA_TYPE_WORD, 0);

for( i = 0; i < SOURCE_BUFFER_SIZE_32b; i++){
for (i = 0; i < SOURCE_BUFFER_SIZE_32b; i++)
{
errors += destin_32b[i] != CONST_VALUE_32B;
}

dma_fill_16b( &source_16b, &value_16b, SOURCE_BUFFER_SIZE_16b, 0);
dma_copy_16b( &destin_16b, &source_16b, SOURCE_BUFFER_SIZE_16b, 0);
dma_fill((uint32_t)source_16b, (uint32_t)&value_16b, SOURCE_BUFFER_SIZE_16b, 0, DMA_DATA_TYPE_HALF_WORD, DMA_DATA_TYPE_HALF_WORD, 0);
dma_copy((uint32_t)destin_16b, (uint32_t)source_16b, SOURCE_BUFFER_SIZE_16b, 0, DMA_DATA_TYPE_HALF_WORD, DMA_DATA_TYPE_HALF_WORD, 0);

for( i = 0; i < SOURCE_BUFFER_SIZE_16b; i++){
for (i = 0; i < SOURCE_BUFFER_SIZE_16b; i++)
{
errors += destin_16b[i] != CONST_VALUE_16B;
}

dma_fill_8b( &source_8b, &value_8b, SOURCE_BUFFER_SIZE_8b, 0);
dma_copy_8b( &destin_8b, &source_8b, SOURCE_BUFFER_SIZE_8b, 0);
dma_fill((uint32_t)source_8b, (uint32_t)&value_8b, SOURCE_BUFFER_SIZE_8b, 0, DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_BYTE, 0);
dma_copy((uint32_t)destin_8b, (uint32_t)source_8b, SOURCE_BUFFER_SIZE_8b, 0, DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_BYTE, 0);

for( i = 0; i < SOURCE_BUFFER_SIZE_8b; i++){
for (i = 0; i < SOURCE_BUFFER_SIZE_8b; i++)
{
errors += destin_8b[i] != CONST_VALUE_8B;
}

PRINTF("Errors:%d\n\r",errors );
dma_fill((uint32_t)neg_source_16b, (uint32_t)&neg_value_8b, SOURCE_BUFFER_SIZE_32b, 0, DMA_DATA_TYPE_BYTE, DMA_DATA_TYPE_HALF_WORD, 1);
dma_copy((uint32_t)neg_destin_32b, (uint32_t)neg_source_16b, SOURCE_BUFFER_SIZE_32b, 0, DMA_DATA_TYPE_HALF_WORD, DMA_DATA_TYPE_WORD, 1);

for (i = 0; i < SOURCE_BUFFER_SIZE_32b; i++)
{
errors += destin_32b[i] != CONST_VALUE_32B;
}

PRINTF("Errors:%d\n\r", errors);

return errors ? EXIT_FAILURE : EXIT_SUCCESS;
}
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