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ocxl: control via sysfs whether the FPGA is reloaded on a link reset
Some opencapi FPGA images allow to control if the FPGA should be reloaded on the next adapter reset. If it is supported, the image specifies it through a Vendor Specific DVSEC in the config space of function 0. Signed-off-by: Philippe Bergheaud <[email protected]> Signed-off-by: Frederic Barrat <[email protected]> Reviewed-by: Andrew Donnellan <[email protected]> Signed-off-by: Michael Ellerman <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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Original file line number | Diff line number | Diff line change |
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@@ -33,3 +33,14 @@ Date: January 2018 | |
Contact: [email protected] | ||
Description: read/write | ||
Give access the global mmio area for the AFU | ||
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What: /sys/class/ocxl/<afu name>/reload_on_reset | ||
Date: February 2020 | ||
Contact: [email protected] | ||
Description: read/write | ||
Control whether the FPGA is reloaded on a link reset. Enabled | ||
through a vendor-specific logic block on the FPGA. | ||
0 Do not reload FPGA image from flash | ||
1 Reload FPGA image from flash | ||
unavailable | ||
The device does not support this capability |
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