bump antlr4 (chipsalliance#1936)

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
vjaligam5 · Nov 16, 2020 · 4dd45a8 · 4dd45a8
1 parent b249814
commit 4dd45a8
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/build.sbt b/build.sbt
@@ -85,7 +85,7 @@ lazy val antlrSettings = Seq(
   antlr4GenVisitor in Antlr4 := true,
   antlr4GenListener in Antlr4 := false,
   antlr4PackageName in Antlr4 := Option("firrtl.antlr"),
-  antlr4Version in Antlr4 := "4.7.1",
+  antlr4Version in Antlr4 := "4.8",
   javaSource in Antlr4 := (sourceManaged in Compile).value
 )
 

diff --git a/build.sc b/build.sc
@@ -94,7 +94,7 @@ class firrtlCrossModule(val crossScalaVersion: String) extends CrossSbtModule wi
   }
 
   /* antlr4 */
-  def antlr4Version = "4.7.1"
+  def antlr4Version = "4.8"
 
   def antlrSource = T.source {
     millSourcePath / "src" / "main" / "antlr4" / "FIRRTL.g4"