Finished expand-whens. Removed letrec also, a while ago

TODO

@@ -1,10 +1,7 @@
 TODO 
-   when calculating writeenables, use assignment
-   when calculating read enables, scan list
    change parser to use <> syntax (and update all tests)
 
    Figure out how widths propogate for all updated primops (Adam)
-   Remove letrec. Add to expressions: Register(input,en), ReadPort(mem,index,enable), WritePort(mem,index,enable) (Patrick)
    Add bit-reduce-and etc to primops (Jonathan)
    Write pass to rename identifiers (alpha-transform) (Adam)
    Add partial bulk connect (Scott, Stephen)
@@ -32,6 +29,7 @@ TODO
 Checks:
    Subfields are only on bundles, before type inference 
    after adding dynamic assertions, insert bounds check with accessor expansion
+   all things only assigned to once
 
 Tests:
    Error if declare anything other than module in circuit

notes/notes.03.18.15.txt

@@ -45,21 +45,28 @@ if w is a wire:
 merge {r=>x, w=>y} with {r=>x} under p : {r=>svmux(p,x,x), w=>y}
 
 if s is a reg:
-merge {r=>x,s=>y} with {r=>x} under p : {r=>svmux(p,x,x), s=>svmux(p,y,void)} ;this is to correctly calculate the ENABLE signal! when actually calculating the input, we will reduce it
+merge {r=>x,s=>y} with {r=>x} under p : {r=>svmux(p,x,x), s=>svmux(p,y,void)} 
+;this is to correctly calculate the ENABLE signal! when actually calculating the input, we will reduce it
+;actually, since we will be doing the reducing anyways, we might as well not do anything different for wires, 
+;  and instead do the reduction step separately
 
 wire r     {r=>VOID}
 r := x     {r=>x}
 when p     {r=>x}
   reg s    {r=>x,s=>VOID}
   s := y   {r=>x,s=>y}
   wire w   {r=>x,s=>y,w=>VOID}
+else       {r=>x}
+  reg s    {r=>x,s=>VOID}
+  wire w   {r=>x,s=>VOID,w=>VOID}
+  w := z   {r=>x,s=>VOID,w=>z}
   w := y   {r=>x,s=>y,w=>y}
 else 
   emptystmt {r=>x}
 ;merge table-c with table-a
 ;get unique keys of table-a + table-c
 ; (r,s,w)
-{r=>(p?x:x),s=>
+{r=>(p?x:x),s=>(p?y:VOID),w=>(p?y:VOID)}
 
 
 

src/main/stanza/ir-utils.stanza

@@ -139,6 +139,7 @@ defmethod print (o:OutputStream, e:Expression) :
          print(o, ")")
       (e:ReadPort) : print-all(o, ["ReadPort(" mem(e) ", " index(e) ", " enable(e) ")"])
       (e:WritePort) : print-all(o, ["WritePort(" mem(e) ", " index(e) ", " enable(e) ")"])
+      (e:Register) : print-all(o, ["Register(" value(e) ", " enable(e) ")"])
    print-debug(o,e)
 
 defmethod print (o:OutputStream, c:Stmt) :