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uvm-testbench-tutorial-simple-adder
uvm-testbench-tutorial-simple-adder PublicForked from naragece/uvm-testbench-tutorial-simple-adder
A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology
SystemVerilog
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compilebox
compilebox PublicForked from remoteinterview/compilebox
Compile and run user-submitted code in a docker based sandbox.
JavaScript
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