rtl8723be: Add L1 latency to rtl8723be

Signed-off-by: Larry Finger <[email protected]>
w179962443 · Feb 22, 2018 · 1969725 · 1969725
1 parent 0588ac0
commit 1969725
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Showing 3 changed files with 29 additions and 1 deletion.
diff --git a/rtl8723be/hw.c b/rtl8723be/hw.c
@@ -1126,7 +1126,8 @@ static void _rtl8723be_enable_aspm_back_door(struct ieee80211_hw *hw)
 
 	/* Configuration Space offset 0x70f BIT7 is used to control L0S */
 	tmp8 = _rtl8723be_dbi_read(rtlpriv, 0x70f);
-	_rtl8723be_dbi_write(rtlpriv, 0x70f, tmp8 | BIT(7));
+	_rtl8723be_dbi_write(rtlpriv, 0x70f, tmp8 | BIT(7) |
+			     ASPM_L1_LATENCY << 3);
 
 	/* Configuration Space offset 0x719 Bit3 is for L1
 	 * BIT4 is for clock request

diff --git a/rtl8723be/phy.c b/rtl8723be/phy.c
@@ -1472,6 +1472,7 @@ static u8 _rtl8723be_phy_path_a_iqk(struct ieee80211_hw *hw)
 	/* leave IQK mode */
 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
 	/* switch to path A */
+	pr_info("**** %s: reg 0x948 0x0\n", __func__);
 	rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000000);
 	/* enable path A PA in TXIQK mode */
 	rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
@@ -1546,6 +1547,7 @@ static u8 _rtl8723be_phy_path_a_rx_iqk(struct ieee80211_hw *hw)
 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
 
 	/* switch to path A */
+	pr_info("**** %s: reg 0x948 0x0\n", __func__);
 	rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000000);
 
 	/* 1 Get TXIMR setting */
@@ -1692,6 +1694,7 @@ static u8 _rtl8723be_phy_path_b_iqk(struct ieee80211_hw *hw)
 	/* leave IQK mode */
 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
 	/* switch to path B */
+	pr_info("**** %s: reg 0x948 0x280\n", __func__);
 	rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000280);
 
 	/* enable path B PA in TXIQK mode */
@@ -1765,6 +1768,7 @@ static u8 _rtl8723be_phy_path_b_rx_iqk(struct ieee80211_hw *hw)
 	/* leave IQK mode */
 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
 	/* switch to path B */
+	pr_info("**** %s: reg 0x948 0x280\n", __func__);
 	rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000280);
 
 	/* 1 Get TXIMR setting */
@@ -2160,6 +2164,7 @@ static void _rtl8723be_phy_iq_calibrate(struct ieee80211_hw *hw,
 						  rtlphy->iqk_bb_backup,
 						  IQK_BB_REG_NUM);
 
+		pr_info("**** %s: reg 0x948 0x%x\n", __func__, path_sel_bb);
 		rtl_set_bbreg(hw, 0x948, MASKDWORD, path_sel_bb);
 		/*rtl_set_rfreg(hw, RF90_PATH_B, 0xb0, 0xfffff, path_sel_rf);*/
 
@@ -2402,6 +2407,7 @@ void rtl8723be_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
 	rtl8723_save_adda_registers(hw, iqk_bb_reg,
 				    rtlphy->iqk_bb_backup, 9);
 
+	pr_info("**** %s: reg 0x948 0x%x\n", __func__, path_sel_bb);
 	rtl_set_bbreg(hw, 0x948, MASKDWORD, path_sel_bb);
 	/* rtl_set_rfreg(hw, RF90_PATH_A, 0xb0, 0xfffff, path_sel_rf); */
 

diff --git a/rtl8723be/phy.c.rej b/rtl8723be/phy.c.rej
@@ -0,0 +1,21 @@
+--- rtl8723be/phy.c
++++ rtl8723be/phy.c
+@@ -520,12 +520,16 @@ static bool _rtl8723be_phy_bb8723b_config_parafile(struct ieee80211_hw *hw)
+
+ 	/* switch ant to BT */
+ 	if (rtlpriv->rtlhal.interface == INTF_USB) {
++		pr_info("**** %s: reg 0x948 0x0\n", __func__);
+ 		rtl_write_dword(rtlpriv, 0x948, 0x0);
+ 	} else {
+-		if (rtlpriv->btcoexist.btc_info.single_ant_path == 0)
++		if (rtlpriv->btcoexist.btc_info.single_ant_path == 0) {
++			pr_info("**** %s: single_ant_path %d, reg 0x948 0x280\n", __func__, rtlpriv->btcoexist.btc_info.single_ant_path);
+ 			rtl_write_dword(rtlpriv, 0x948, 0x280);
+-		else
++		} else {
++			pr_info("**** %s: single_ant_path %d, reg 0x948 0x0\n", __func__, rtlpriv->btcoexist.btc_info.single_ant_path);
+ 			rtl_write_dword(rtlpriv, 0x948, 0x0);
++		}
+ 	}
+
+ 	rtstatus = _rtl8723be_phy_config_bb_with_headerfile(hw,