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Merge tag 'cxl-for-6.7' of git://git.kernel.org/pub/scm/linux/kernel/…
…git/cxl/cxl Pull CXL (Compute Express Link) updates from Dan Williams: "The main new functionality this time is work to allow Linux to natively handle CXL link protocol errors signalled via PCIe AER for current generation CXL platforms. This required some enlightenment of the PCIe AER core to workaround the fact that current generation RCH (Restricted CXL Host) platforms physically hide topology details and registers via a mechanism called RCRB (Root Complex Register Block). The next major highlight is reworks to address bugs in parsing region configurations for next generation VH (Virtual Host) topologies. The old broken algorithm is replaced with a simpler one that significantly increases the number of region configurations supported by Linux. This is again relevant for error handling so that forward and reverse address translation of memory errors can be carried out by Linux for memory regions instantiated by platform firmware. As for other cross-tree work, the ACPI table parsing code has been refactored for reuse parsing the "CDAT" structure which is an ACPI-like data structure that is reported by CXL devices. That work is in preparation for v6.8 support for CXL QoS. Think of this as dynamic generation of NUMA node topology information generated by Linux rather than platform firmware. Lastly, a number of internal object lifetime issues have been resolved along with misc. fixes and feature updates (decoders_committed sysfs ABI). Summary: - Add support for RCH (Restricted CXL Host) Error recovery - Fix several region assembly bugs - Fix mem-device lifetime issues relative to the sanitize command and RCH topology. - Refactor ACPI table parsing for CDAT parsing re-use in preparation for CXL QOS support" * tag 'cxl-for-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl: (50 commits) lib/fw_table: Remove acpi_parse_entries_array() export cxl/pci: Change CXL AER support check to use native AER cxl/hdm: Remove broken error path cxl/hdm: Fix && vs || bug acpi: Move common tables helper functions to common lib cxl: Add support for reading CXL switch CDAT table cxl: Add checksum verification to CDAT from CXL cxl: Export QTG ids from CFMWS to sysfs as qos_class attribute cxl: Add decoders_committed sysfs attribute to cxl_port cxl: Add cxl_decoders_committed() helper cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devm cxl/core/regs: Rename phys_addr in cxl_map_component_regs() PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler cxl/pci: Disable root port interrupts in RCH mode cxl/pci: Add RCH downstream port error logging cxl/pci: Map RCH downstream AER registers for logging protocol errors cxl/pci: Update CXL error logging to use RAS register address PCI/AER: Refactor cper_print_aer() for use by CXL driver module cxl/pci: Add RCH downstream port AER register discovery ...
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@@ -178,6 +178,21 @@ Description: | |
hardware decoder target list. | ||
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What: /sys/bus/cxl/devices/portX/decoders_committed | ||
Date: October, 2023 | ||
KernelVersion: v6.7 | ||
Contact: [email protected] | ||
Description: | ||
(RO) A memory device is considered active when any of its | ||
decoders are in the "committed" state (See CXL 3.0 8.2.4.19.7 | ||
CXL HDM Decoder n Control Register). Hotplug and destructive | ||
operations like "sanitize" are blocked while device is actively | ||
decoding a Host Physical Address range. Note that this number | ||
may be elevated without any regionX objects active or even | ||
enumerated, as this may be due to decoders established by | ||
platform firwmare or a previous kernel (kexec). | ||
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What: /sys/bus/cxl/devices/decoderX.Y | ||
Date: June, 2021 | ||
KernelVersion: v5.14 | ||
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provided it is currently idle / not bound to a driver. | ||
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What: /sys/bus/cxl/devices/decoderX.Y/qos_class | ||
Date: May, 2023 | ||
KernelVersion: v6.5 | ||
Contact: [email protected] | ||
Description: | ||
(RO) For CXL host platforms that support "QoS Telemmetry" this | ||
root-decoder-only attribute conveys a platform specific cookie | ||
that identifies a QoS performance class for the CXL Window. | ||
This class-id can be compared against a similar "qos_class" | ||
published for each memory-type that an endpoint supports. While | ||
it is not required that endpoints map their local memory-class | ||
to a matching platform class, mismatches are not recommended and | ||
there are platform specific side-effects that may result. | ||
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What: /sys/bus/cxl/devices/regionZ/uuid | ||
Date: May, 2022 | ||
KernelVersion: v6.0 | ||
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@@ -294,6 +294,8 @@ F: drivers/pnp/pnpacpi/ | |
F: include/acpi/ | ||
F: include/linux/acpi.h | ||
F: include/linux/fwnode.h | ||
F: include/linux/fw_table.h | ||
F: lib/fw_table.c | ||
F: tools/power/acpi/ | ||
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ACPI APEI | ||
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@@ -5244,6 +5246,7 @@ L: [email protected] | |
S: Maintained | ||
F: drivers/cxl/ | ||
F: include/uapi/linux/cxl_mem.h | ||
F: tools/testing/cxl/ | ||
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COMPUTE EXPRESS LINK PMU (CPMU) | ||
M: Jonathan Cameron <[email protected]> | ||
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