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Merge tag 'drivers-5.17' of git://git.kernel.org/pub/scm/linux/kernel…
…/git/soc/soc
Pull ARM SoC driver updates from Arnd Bergmann:
"There are cleanups and minor bugfixes across several SoC specific
drivers, for Qualcomm, Samsung, NXP i.MX, AT91, Tegra, Keystone,
Renesas, ZynqMP
Noteworthy new features are:
- The op-tee firmware driver gains support for asynchronous
notifications from secure-world firmware.
- Qualcomm platforms gain support for new SoC types in various
drivers: power domain, cache controller, RPM sleep, soc-info
- Samsung SoC drivers gain support for new SoCs in ChipID and PMU, as
well as a new USIv2 driver that handles various types of serial
communiction (uart, i2c, spi)
- Renesas adds support for R-Car S4-8 (R8A779F0) in multiple drivers,
as well as memory controller support for RZ/G2L (R9A07G044).
- Apple M1 gains support for the PMGR power management driver"
* tag 'drivers-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (94 commits)
soc: qcom: rpmh-rsc: Fix typo in a comment
soc: qcom: socinfo: Add SM6350 and SM7225
dt-bindings: arm: msm: Don't mark LLCC interrupt as required
dt-bindings: firmware: scm: Add SM6350 compatible
dt-bindings: arm: msm: Add LLCC for SM6350
soc: qcom: rpmhpd: Sort power-domain definitions and lists
soc: qcom: rpmhpd: Remove mx/cx relationship on sc7280
soc: qcom: rpmhpd: Rename rpmhpd struct names
soc: qcom: rpmhpd: sm8450: Add the missing .peer for sm8450_cx_ao
soc: qcom: socinfo: add SM8450 ID
soc: qcom: rpmhpd: Add SM8450 power domains
dt-bindings: power: rpmpd: Add SM8450 to rpmpd binding
soc: qcom: smem: Update max processor count
dt-bindings: arm: qcom: Document SM8450 SoC and boards
dt-bindings: firmware: scm: Add SM8450 compatible
dt-bindings: arm: cpus: Add kryo780 compatible
soc: qcom: rpmpd: Add support for sm6125
dt-bindings: qcom-rpmpd: Add sm6125 power domains
soc: qcom: aoss: constify static struct thermal_cooling_device_ops
PM: AVS: qcom-cpr: Use div64_ul instead of do_div
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2 changes: 1 addition & 1 deletion
2
...e/bindings/arm/samsung/exynos-chipid.yaml → ...e/bindings/soc/samsung/exynos-chipid.yaml
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159 changes: 159 additions & 0 deletions
159
Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,159 @@ | ||
| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
| %YAML 1.2 | ||
| --- | ||
| $id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml# | ||
| $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
|
|
||
| title: Samsung's Exynos USI (Universal Serial Interface) binding | ||
|
|
||
| maintainers: | ||
| - Sam Protsenko <[email protected]> | ||
| - Krzysztof Kozlowski <[email protected]> | ||
|
|
||
| description: | | ||
| USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C). | ||
| USI shares almost all internal circuits within each protocol, so only one | ||
| protocol can be chosen at a time. USI is modeled as a node with zero or more | ||
| child nodes, each representing a serial sub-node device. The mode setting | ||
| selects which particular function will be used. | ||
| Refer to next bindings documentation for information on protocol subnodes that | ||
| can exist under USI node: | ||
| [1] Documentation/devicetree/bindings/serial/samsung_uart.yaml | ||
| [2] Documentation/devicetree/bindings/i2c/i2c-exynos5.txt | ||
| [3] Documentation/devicetree/bindings/spi/spi-samsung.txt | ||
| properties: | ||
| $nodename: | ||
| pattern: "^usi@[0-9a-f]+$" | ||
|
|
||
| compatible: | ||
| enum: | ||
| - samsung,exynos850-usi # for USIv2 (Exynos850, ExynosAutoV9) | ||
|
|
||
| reg: true | ||
|
|
||
| clocks: true | ||
|
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||
| clock-names: true | ||
|
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||
| ranges: true | ||
|
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||
| "#address-cells": | ||
| const: 1 | ||
|
|
||
| "#size-cells": | ||
| const: 1 | ||
|
|
||
| samsung,sysreg: | ||
| $ref: /schemas/types.yaml#/definitions/phandle-array | ||
| description: | ||
| Should be phandle/offset pair. The phandle to System Register syscon node | ||
| (for the same domain where this USI controller resides) and the offset | ||
| of SW_CONF register for this USI controller. | ||
|
|
||
| samsung,mode: | ||
| $ref: /schemas/types.yaml#/definitions/uint32 | ||
| description: | ||
| Selects USI function (which serial protocol to use). Refer to | ||
| <include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values. | ||
|
|
||
| samsung,clkreq-on: | ||
| type: boolean | ||
| description: | ||
| Enable this property if underlying protocol requires the clock to be | ||
| continuously provided without automatic gating. As suggested by SoC | ||
| manual, it should be set in case of SPI/I2C slave, UART Rx and I2C | ||
| multi-master mode. Usually this property is needed if USI mode is set | ||
| to "UART". | ||
|
|
||
| This property is optional. | ||
|
|
||
| patternProperties: | ||
| # All other properties should be child nodes | ||
| "^(serial|spi|i2c)@[0-9a-f]+$": | ||
| type: object | ||
| description: Child node describing underlying USI serial protocol | ||
|
|
||
| required: | ||
| - compatible | ||
| - ranges | ||
| - "#address-cells" | ||
| - "#size-cells" | ||
| - samsung,sysreg | ||
| - samsung,mode | ||
|
|
||
| if: | ||
| properties: | ||
| compatible: | ||
| contains: | ||
| enum: | ||
| - samsung,exynos850-usi | ||
|
|
||
| then: | ||
| properties: | ||
| reg: | ||
| maxItems: 1 | ||
|
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||
| clocks: | ||
| items: | ||
| - description: Bus (APB) clock | ||
| - description: Operating clock for UART/SPI/I2C protocol | ||
|
|
||
| clock-names: | ||
| items: | ||
| - const: pclk | ||
| - const: ipclk | ||
|
|
||
| required: | ||
| - reg | ||
| - clocks | ||
| - clock-names | ||
|
|
||
| else: | ||
| properties: | ||
| reg: false | ||
| clocks: false | ||
| clock-names: false | ||
| samsung,clkreq-on: false | ||
|
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||
| additionalProperties: false | ||
|
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||
| examples: | ||
| - | | ||
| #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| #include <dt-bindings/soc/samsung,exynos-usi.h> | ||
| usi0: usi@138200c0 { | ||
| compatible = "samsung,exynos850-usi"; | ||
| reg = <0x138200c0 0x20>; | ||
| samsung,sysreg = <&sysreg_peri 0x1010>; | ||
| samsung,mode = <USI_V2_UART>; | ||
| samsung,clkreq-on; /* needed for UART mode */ | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
| ranges; | ||
| clocks = <&cmu_peri 32>, <&cmu_peri 31>; | ||
| clock-names = "pclk", "ipclk"; | ||
| serial_0: serial@13820000 { | ||
| compatible = "samsung,exynos850-uart"; | ||
| reg = <0x13820000 0xc0>; | ||
| interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; | ||
| clocks = <&cmu_peri 32>, <&cmu_peri 31>; | ||
| clock-names = "uart", "clk_uart_baud0"; | ||
| status = "disabled"; | ||
| }; | ||
| hsi2c_0: i2c@13820000 { | ||
| compatible = "samsung,exynosautov9-hsi2c"; | ||
| reg = <0x13820000 0xc0>; | ||
| interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| clocks = <&cmu_peri 32>, <&cmu_peri 31>; | ||
| clock-names = "hsi2c_pclk", "hsi2c"; | ||
| status = "disabled"; | ||
| }; | ||
| }; |
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