AArch64: allow 64-bit access to sysregs.

Although all the registers are actually 32-bits, I think we have to assume the
high 32-bits could be RES0 (the ARM ARM is unclear). If so, reading as a 32-bit
register can require extra zero extension operations.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@266212 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Sema/SemaChecking.cpp

@@ -1155,7 +1155,7 @@ bool Sema::CheckAArch64BuiltinFunctionCall(unsigned BuiltinID,
 
   if (BuiltinID == AArch64::BI__builtin_arm_rsr64 ||
       BuiltinID == AArch64::BI__builtin_arm_wsr64)
-    return SemaBuiltinARMSpecialReg(BuiltinID, TheCall, 0, 5, false);
+    return SemaBuiltinARMSpecialReg(BuiltinID, TheCall, 0, 5, true);
 
   if (BuiltinID == AArch64::BI__builtin_arm_rsr ||
       BuiltinID == AArch64::BI__builtin_arm_rsrp ||

test/Sema/aarch64-special-register.c

@@ -13,7 +13,7 @@ void wsrp_1(void *v) {
 }
 
 void wsr64_1(unsigned long v) {
-  __builtin_arm_wsr64("sysreg", v); //expected-error {{invalid special register for builtin}}
+  __builtin_arm_wsr64("sysreg", v);
 }
 
 unsigned rsr_1() {
@@ -25,7 +25,7 @@ void *rsrp_1() {
 }
 
 unsigned long rsr64_1() {
-  return __builtin_arm_rsr64("sysreg"); //expected-error {{invalid special register for builtin}}
+  return __builtin_arm_rsr64("sysreg");
 }
 
 void wsr_2(unsigned v) {