Fixing some particularly bad /W4.

premake5.lua

@@ -70,8 +70,13 @@ filter("platforms:Windows")
   linkoptions({"/ignore:4006", "/ignore:4221"})
   -- Enable multiprocessor compiles (requires Minimal Rebuild to be disabled).
   buildoptions({
-    "/MP",              -- Multiprocessor compilation.
-    "/wd4100",          -- Unreferenced parameters are ok.
+    "/MP",      -- Multiprocessor compilation.
+    "/wd4100",  -- Unreferenced parameters are ok.
+    "/wd4201",  -- Nameless struct/unions are ok.
+    "/wd4512",  -- 'assignment operator was implicitly defined as deleted'.
+    "/wd4127",  -- 'conditional expression is constant'.
+    "/wd4324",  -- 'structure was padded due to alignment specifier'.
+    "/wd4189",  -- 'local variable is initialized but not referenced'.
   })
   flags({
     "NoMinimalRebuild", -- Required for /MP above.

src/xenia/cpu/backend/x64/x64_sequences.cc

@@ -212,8 +212,7 @@ struct ValueOp : Op<ValueOp<T, KEY_TYPE, REG_TYPE, CONST_TYPE>, KEY_TYPE> {
   bool operator==(const Xbyak::Reg& b) const { return IsEqual(b); }
   bool operator!=(const Xbyak::Reg& b) const { return !IsEqual(b); }
   void Load(const Instr::Op& op) {
-    const Value* value = op.value;
-    this->value = value;
+    value = op.value;
     is_constant = value->IsConstant();
     if (!is_constant) {
       X64Emitter::SetupReg(value, reg_);

src/xenia/cpu/compiler/passes/data_flow_analysis_pass.cc

@@ -55,7 +55,7 @@ bool DataFlowAnalysisPass::Run(HIRBuilder* builder) {
 uint32_t DataFlowAnalysisPass::LinearizeBlocks(HIRBuilder* builder) {
   // TODO(benvanik): actually do this - we cheat now knowing that they are in
   //     sequential order.
-  uint32_t block_ordinal = 0;
+  uint16_t block_ordinal = 0;
   auto block = builder->first_block();
   while (block) {
     block->ordinal = block_ordinal++;

src/xenia/cpu/compiler/passes/finalization_pass.cc

@@ -34,7 +34,7 @@ bool FinalizationPass::Run(HIRBuilder* builder) {
 
   auto arena = builder->arena();
 
-  uint32_t block_ordinal = 0;
+  uint16_t block_ordinal = 0;
   auto block = builder->first_block();
   while (block) {
     block->ordinal = block_ordinal++;

src/xenia/cpu/compiler/passes/register_allocation_pass.cc

@@ -77,7 +77,7 @@ bool RegisterAllocationPass::Run(HIRBuilder* builder) {
   // Really, it'd just be nice to have someone who knew what they
   // were doing lower SSA and do this right.
 
-  uint32_t block_ordinal = 0;
+  uint16_t block_ordinal = 0;
   uint32_t instr_ordinal = 0;
   auto block = builder->first_block();
   while (block) {
@@ -212,27 +212,27 @@ void RegisterAllocationPass::AdvanceUses(Instr* instr) {
       break;
     }
     auto& upcoming_uses = usage_set->upcoming_uses;
-    for (int i = 0; i < upcoming_uses.size();) {
-      auto& upcoming_use = upcoming_uses.at(i);
+    for (size_t j = 0; j < upcoming_uses.size();) {
+      auto& upcoming_use = upcoming_uses.at(j);
       if (!upcoming_use.use) {
         // No uses at all - we can remove right away.
         // This comes up from instructions where the dest is never used,
         // like the ATOMIC ops.
         MarkRegAvailable(upcoming_use.value->reg);
-        upcoming_uses.erase(upcoming_uses.begin() + i);
+        upcoming_uses.erase(upcoming_uses.begin() + j);
         // i remains the same.
         continue;
       }
       if (upcoming_use.use->instr != instr) {
         // Not yet at this instruction.
-        ++i;
+        ++j;
         continue;
       }
       // The use is from this instruction.
       if (!upcoming_use.use->next) {
         // Last use of the value. We can retire it now.
         MarkRegAvailable(upcoming_use.value->reg);
-        upcoming_uses.erase(upcoming_uses.begin() + i);
+        upcoming_uses.erase(upcoming_uses.begin() + j);
         // i remains the same.
         continue;
       } else {
@@ -245,7 +245,7 @@ void RegisterAllocationPass::AdvanceUses(Instr* instr) {
         }
         // Remove the iterator.
         auto value = upcoming_use.value;
-        upcoming_uses.erase(upcoming_uses.begin() + i);
+        upcoming_uses.erase(upcoming_uses.begin() + j);
         assert_true(next_use->instr->block == instr->block);
         assert_true(value->def->block == instr->block);
         upcoming_uses.emplace_back(value, next_use);

src/xenia/cpu/export_resolver.h

@@ -23,30 +23,30 @@ struct ExportTag {
   typedef uint32_t type;
 
   // Export is implemented in some form and can be used.
-  static const type kImplemented = 1 << 0;
+  static const type kImplemented = 1u << 0;
   // Export is a stub and is probably bad.
-  static const type kStub = 1 << 1;
+  static const type kStub = 1u << 1;
   // Export is known to cause problems, or may not be complete.
-  static const type kSketchy = 1 << 2;
+  static const type kSketchy = 1u << 2;
   // Export is called *a lot*.
-  static const type kHighFrequency = 1 << 3;
+  static const type kHighFrequency = 1u << 3;
   // Export is important and should always be logged.
-  static const type kImportant = 1 << 4;
-
-  static const type kThreading = 1 << 10;
-  static const type kInput = 1 << 11;
-  static const type kAudio = 1 << 12;
-  static const type kVideo = 1 << 13;
-  static const type kFileSystem = 1 << 14;
-  static const type kModules = 1 << 15;
-  static const type kUserProfiles = 1 << 16;
-  static const type kNetworking = 1 << 17;
-  static const type kMemory = 1 << 18;
+  static const type kImportant = 1u << 4;
+
+  static const type kThreading = 1u << 10;
+  static const type kInput = 1u << 11;
+  static const type kAudio = 1u << 12;
+  static const type kVideo = 1u << 13;
+  static const type kFileSystem = 1u << 14;
+  static const type kModules = 1u << 15;
+  static const type kUserProfiles = 1u << 16;
+  static const type kNetworking = 1u << 17;
+  static const type kMemory = 1u << 18;
 
   // Export will be logged on each call.
-  static const type kLog = 1 << 30;
+  static const type kLog = 1u << 30;
   // Export's result will be logged on each call.
-  static const type kLogResult = 1 << 31;
+  static const type kLogResult = 1u << 31;
 };
 
 // DEPRECATED

src/xenia/cpu/frontend/ppc_context.h

@@ -40,7 +40,7 @@ namespace frontend {
 // 100: invalid
 // 128-256: VR
 
-#pragma pack(push, 4)
+#pragma pack(push, 8)
 typedef struct alignas(64) PPCContext_s {
   // Must be stored at 0x0 for now.
   // TODO(benvanik): find a nice way to describe this to the JIT.
@@ -49,9 +49,11 @@ typedef struct alignas(64) PPCContext_s {
   uint8_t* virtual_membase;
 
   // Most frequently used registers first.
-  uint64_t r[32];  // General purpose registers
-  uint64_t lr;     // Link register
-  uint64_t ctr;    // Count register
+  uint64_t lr;      // Link register
+  uint64_t ctr;     // Count register
+  uint64_t r[32];   // General purpose registers
+  double f[32];     // Floating-point registers
+  vec128_t v[128];  // VMX128 vector registers
 
   // XER register
   // Split to make it easier to do individual updates.
@@ -188,9 +190,6 @@ typedef struct alignas(64) PPCContext_s {
 
   uint8_t vscr_sat;
 
-  double f[32];     // Floating-point registers
-  vec128_t v[128];  // VMX128 vector registers
-
   // uint32_t get_fprf() {
   //   return fpscr.value & 0x000F8000;
   // }
@@ -216,11 +215,15 @@ typedef struct alignas(64) PPCContext_s {
 
   uint8_t* physical_membase;
 
+  // Keep the struct padded out to 64b total.
+  uint8_t _padding[8];
+
   void SetRegFromString(const char* name, const char* value);
   bool CompareRegWithString(const char* name, const char* value,
                             char* out_value, size_t out_value_size);
 } PPCContext;
 #pragma pack(pop)
+static_assert(sizeof(PPCContext) % 64 == 0, "64b padded");
 
 }  // namespace frontend
 }  // namespace cpu

src/xenia/cpu/frontend/ppc_instr.cc

@@ -295,10 +295,11 @@ void InstrAccessBits::Dump(std::string& out_str) {
   out_str = str.str();
 }
 
-void InstrDisasm::Init(const char* name, const char* info, uint32_t flags) {
-  this->name = name;
-  this->info = info;
-  this->flags = flags;
+void InstrDisasm::Init(const char* new_name, const char* new_info,
+                       uint32_t new_flags) {
+  name = new_name;
+  info = new_info;
+  flags = new_flags;
 }
 
 void InstrDisasm::AddLR(InstrRegister::Access access) {}

src/xenia/cpu/frontend/ppc_instr.h

@@ -483,7 +483,7 @@ class InstrDisasm {
   const char* info;
   uint32_t flags;
 
-  void Init(const char* name, const char* info, uint32_t flags);
+  void Init(const char* new_name, const char* new_info, uint32_t new_flags);
   void AddLR(InstrRegister::Access access);
   void AddCTR(InstrRegister::Access access);
   void AddCR(uint32_t bf, InstrRegister::Access access);

src/xenia/cpu/hir/hir_builder.cc

@@ -388,7 +388,7 @@ void HIRBuilder::InsertLabel(Label* label, Instr* prev_instr) {
   Block* next_block = prev_instr->block->next;
 
   Block* new_block = arena_->Alloc<Block>();
-  new_block->ordinal = -1;
+  new_block->ordinal = UINT16_MAX;
   new_block->incoming_values = nullptr;
   new_block->arena = arena_;
   new_block->prev = prev_block;
@@ -466,10 +466,10 @@ void HIRBuilder::AddEdge(Block* src, Block* dest, uint32_t flags) {
 
   if (dest_was_dominated) {
     // If dest was previously dominated it no longer is.
-    auto edge = dest->incoming_edge_head;
-    while (edge) {
-      edge->flags &= ~Edge::DOMINATES;
-      edge = edge->incoming_next;
+    auto incoming_edge = dest->incoming_edge_head;
+    while (incoming_edge) {
+      incoming_edge->flags &= ~Edge::DOMINATES;
+      incoming_edge = incoming_edge->incoming_next;
     }
   }
 }
@@ -633,7 +633,7 @@ void HIRBuilder::MergeAdjacentBlocks(Block* left, Block* right) {
 
 Block* HIRBuilder::AppendBlock() {
   Block* block = arena_->Alloc<Block>();
-  block->ordinal = -1;
+  block->ordinal = UINT16_MAX;
   block->incoming_values = nullptr;
   block->arena = arena_;
   block->next = NULL;
@@ -690,7 +690,7 @@ Instr* HIRBuilder::AppendInstr(const OpcodeInfo& opcode_info, uint16_t flags,
   if (!block->instr_head) {
     block->instr_head = instr;
   }
-  instr->ordinal = -1;
+  instr->ordinal = UINT32_MAX;
   instr->block = block;
   instr->opcode = &opcode_info;
   instr->flags = flags;
@@ -824,15 +824,15 @@ void HIRBuilder::TrapTrue(Value* cond, uint16_t trap_code) {
   EndBlock();
 }
 
-void HIRBuilder::Call(FunctionInfo* symbol_info, uint32_t call_flags) {
+void HIRBuilder::Call(FunctionInfo* symbol_info, uint16_t call_flags) {
   Instr* i = AppendInstr(OPCODE_CALL_info, call_flags);
   i->src1.symbol_info = symbol_info;
   i->src2.value = i->src3.value = NULL;
   EndBlock();
 }
 
 void HIRBuilder::CallTrue(Value* cond, FunctionInfo* symbol_info,
-                          uint32_t call_flags) {
+                          uint16_t call_flags) {
   if (cond->IsConstant()) {
     if (cond->IsConstantTrue()) {
       Call(symbol_info, call_flags);
@@ -847,7 +847,7 @@ void HIRBuilder::CallTrue(Value* cond, FunctionInfo* symbol_info,
   EndBlock();
 }
 
-void HIRBuilder::CallIndirect(Value* value, uint32_t call_flags) {
+void HIRBuilder::CallIndirect(Value* value, uint16_t call_flags) {
   ASSERT_CALL_ADDRESS_TYPE(value);
   Instr* i = AppendInstr(OPCODE_CALL_INDIRECT_info, call_flags);
   i->set_src1(value);
@@ -856,7 +856,7 @@ void HIRBuilder::CallIndirect(Value* value, uint32_t call_flags) {
 }
 
 void HIRBuilder::CallIndirectTrue(Value* cond, Value* value,
-                                  uint32_t call_flags) {
+                                  uint16_t call_flags) {
   if (cond->IsConstant()) {
     if (cond->IsConstantTrue()) {
       CallIndirect(value, call_flags);
@@ -907,14 +907,14 @@ void HIRBuilder::SetReturnAddress(Value* value) {
   i->src2.value = i->src3.value = NULL;
 }
 
-void HIRBuilder::Branch(Label* label, uint32_t branch_flags) {
+void HIRBuilder::Branch(Label* label, uint16_t branch_flags) {
   Instr* i = AppendInstr(OPCODE_BRANCH_info, branch_flags);
   i->src1.label = label;
   i->src2.value = i->src3.value = NULL;
   EndBlock();
 }
 
-void HIRBuilder::Branch(Block* block, uint32_t branch_flags) {
+void HIRBuilder::Branch(Block* block, uint16_t branch_flags) {
   if (!block->label_head) {
     // Block needs a label.
     Label* label = NewLabel();
@@ -923,7 +923,7 @@ void HIRBuilder::Branch(Block* block, uint32_t branch_flags) {
   Branch(block->label_head, branch_flags);
 }
 
-void HIRBuilder::BranchTrue(Value* cond, Label* label, uint32_t branch_flags) {
+void HIRBuilder::BranchTrue(Value* cond, Label* label, uint16_t branch_flags) {
   if (cond->IsConstant()) {
     if (cond->IsConstantTrue()) {
       Branch(label, branch_flags);
@@ -938,7 +938,7 @@ void HIRBuilder::BranchTrue(Value* cond, Label* label, uint32_t branch_flags) {
   EndBlock();
 }
 
-void HIRBuilder::BranchFalse(Value* cond, Label* label, uint32_t branch_flags) {
+void HIRBuilder::BranchFalse(Value* cond, Label* label, uint16_t branch_flags) {
   if (cond->IsConstant()) {
     if (cond->IsConstantFalse()) {
       Branch(label, branch_flags);

src/xenia/cpu/hir/hir_builder.h

@@ -83,20 +83,20 @@ class HIRBuilder {
   void Trap(uint16_t trap_code = 0);
   void TrapTrue(Value* cond, uint16_t trap_code = 0);
 
-  void Call(FunctionInfo* symbol_info, uint32_t call_flags = 0);
+  void Call(FunctionInfo* symbol_info, uint16_t call_flags = 0);
   void CallTrue(Value* cond, FunctionInfo* symbol_info,
-                uint32_t call_flags = 0);
-  void CallIndirect(Value* value, uint32_t call_flags = 0);
-  void CallIndirectTrue(Value* cond, Value* value, uint32_t call_flags = 0);
+                uint16_t call_flags = 0);
+  void CallIndirect(Value* value, uint16_t call_flags = 0);
+  void CallIndirectTrue(Value* cond, Value* value, uint16_t call_flags = 0);
   void CallExtern(FunctionInfo* symbol_info);
   void Return();
   void ReturnTrue(Value* cond);
   void SetReturnAddress(Value* value);
 
-  void Branch(Label* label, uint32_t branch_flags = 0);
-  void Branch(Block* block, uint32_t branch_flags = 0);
-  void BranchTrue(Value* cond, Label* label, uint32_t branch_flags = 0);
-  void BranchFalse(Value* cond, Label* label, uint32_t branch_flags = 0);
+  void Branch(Label* label, uint16_t branch_flags = 0);
+  void Branch(Block* block, uint16_t branch_flags = 0);
+  void BranchTrue(Value* cond, Label* label, uint16_t branch_flags = 0);
+  void BranchFalse(Value* cond, Label* label, uint16_t branch_flags = 0);
 
   // phi type_name, Block* b1, Value* v1, Block* b2, Value* v2, etc
 

src/xenia/cpu/hir/instr.cc

@@ -78,9 +78,9 @@ void Instr::MoveBefore(Instr* other) {
   }
 }
 
-void Instr::Replace(const OpcodeInfo* opcode, uint16_t flags) {
-  this->opcode = opcode;
-  this->flags = flags;
+void Instr::Replace(const OpcodeInfo* new_opcode, uint16_t new_flags) {
+  opcode = new_opcode;
+  flags = new_flags;
 
   if (src1_use) {
     src1.value->RemoveUse(src1_use);

src/xenia/cpu/hir/instr.h

@@ -57,7 +57,7 @@ class Instr {
   void set_src3(Value* value);
 
   void MoveBefore(Instr* other);
-  void Replace(const OpcodeInfo* opcode, uint16_t flags);
+  void Replace(const OpcodeInfo* new_opcode, uint16_t new_flags);
   void Remove();
 };