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60 stars written in Verilog
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PicoRV32 - A Size-Optimized RISC-V CPU

Verilog 3,177 767 Updated Jun 27, 2024

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Verilog 2,637 1,019 Updated Mar 24, 2021

Verilog Ethernet components for FPGA implementation

Verilog 2,355 708 Updated Jul 18, 2024

IC design and development should be faster,simpler and more reliable

Verilog 1,876 574 Updated Dec 31, 2021

RTL, Cmodel, and testbench for NVDLA

Verilog 1,763 572 Updated Mar 2, 2022

Must-have verilog systemverilog modules

Verilog 1,671 383 Updated Nov 7, 2024

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog 1,662 574 Updated Dec 16, 2024

HDL libraries and projects

Verilog 1,542 1,528 Updated Dec 16, 2024

Verilog PCI express components

Verilog 1,162 304 Updated Apr 26, 2024

Various HDL (Verilog) IP Cores

Verilog 714 215 Updated Jul 1, 2021

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip …

Verilog 598 116 Updated Nov 13, 2024

A High-performance Timing Analysis Tool for VLSI Systems

Verilog 576 144 Updated May 26, 2023

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器,用于驱动BLDC/PMSM电机。

Verilog 575 179 Updated Sep 15, 2023

AMBA bus lecture material

Verilog 386 128 Updated Jan 21, 2020

Opensource DDR3 Controller

Verilog 231 37 Updated Dec 2, 2024

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Verilog 194 70 Updated Oct 21, 2024
Verilog 142 45 Updated Oct 3, 2020

Advanced Interface Bus (AIB) die-to-die hardware open source

Verilog 128 35 Updated Sep 23, 2024

Fixed Point Math Library for Verilog

Verilog 122 35 Updated Jul 17, 2014

MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.

Verilog 118 36 Updated May 8, 2020

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

Verilog 88 25 Updated Oct 31, 2023

Mathematical Functions in Verilog

Verilog 87 27 Updated Mar 7, 2021

Audio controller (I2S, SPDIF, DAC)

Verilog 81 19 Updated Sep 1, 2019

32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.

Verilog 74 28 Updated Apr 30, 2019

🐥Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.

Verilog 66 26 Updated Nov 22, 2019

PCIE 5.0 Graduation project (Verification Team)

Verilog 54 23 Updated Jan 27, 2024

configurable cordic core in verilog

Verilog 47 15 Updated Jul 17, 2014

Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrated Circuits.

Verilog 42 20 Updated Apr 29, 2015

This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Elliptic Curve Cryptography. This project was implemented using a…

Verilog 30 10 Updated Sep 24, 2018

The CORDIC algorithm implemented in Octave/MATLAB and Verilog

Verilog 28 9 Updated Mar 31, 2015
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60 stars written in Verilog