Stars
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
Verilog Ethernet components for FPGA implementation
IC design and development should be faster,simpler and more reliable
Must-have verilog systemverilog modules
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip …
A High-performance Timing Analysis Tool for VLSI Systems
An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器,用于驱动BLDC/PMSM电机。
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Advanced Interface Bus (AIB) die-to-die hardware open source
Fixed Point Math Library for Verilog
MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
🐥Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
PCIE 5.0 Graduation project (Verification Team)
configurable cordic core in verilog
Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrated Circuits.
This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Elliptic Curve Cryptography. This project was implemented using a…
The CORDIC algorithm implemented in Octave/MATLAB and Verilog