CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.

A Verilog implementation of an ARM series processor supporting: Forwarding, SRAM, and Cache.

A QSPI XiP Flash Controller with a Direct Mapped Cache

AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP

Quad SPI Flash XIP Controller with a direct mapped cache

AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP

Tracks GRLIB GPL from Aeroflex Gaisler, with custom patches

My optimistic - yet unexpectedly successful - attempt to create a LEON3 inside my FPGA boards (ZestSC1, Pano Logic G2)

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip …

32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.

Design an 4x4 matrix divider circuit using Verilog.

Edge Impulse firmware for the Eta Compute ECM3532 AI Sensor development board

source code for ti ultrasonic based water flow meter

An ultrasonic water flowmeter based on transit-time technique

HDLGen-ChatGPT, works in tandem with ChatGPT chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testb…

A huge collection of VHDL/Verilog open-source IP cores scraped from the web

CAN with Flexible Data-rate IP Core developed at Department of Measurement of FEE CTU

HW Design Collateral for Caliptra RoT IP

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

pulp_soc is the core building component of PULP based SoCs

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

Public key generation on Edwards25519 curve with unified point addition

Elliptic curve cryptography coprocessor on FPGA

A VHDL IP for ECC (Elliptic Curve Cryptography) hardware acceleration

Implementation of ECC on FPGA-Zynq7000 SoC

This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Elliptic Curve Cryptography. This project was implemented using a…

Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)

Audio controller (I2S, SPDIF, DAC)

Various HDL (Verilog) IP Cores