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Tags: wwkkww1983/fpga-drive-aximm-pcie

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v2018.2_1

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* fixed linker script issue for Zynq designs

* updated SDK readme

v2018.2

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* added dos2unix instructions

v2017.3

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Fix: petalinux build script now runs petalinux-config after transferr…

…ing config files - this makes sure that the rootfs_config file is registered by the tools

v2017.2

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added more info on PicoZed FMC clock configuration

v2017.1

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added local driver for the PCIe Gen3 core based on driver for the Gen…

…2 core

added SDK applications for the Gen3 designs
modified SDK applications for more comprehensible output
simplified the KCU105 LPC design
BUG FIX: Gen3 designs now set the BASEADDR and HIGHADDR properties of the axi_pcie3 block because Vivado is not propagating them correctly from the address configuration, see https://forums.xilinx.com/t5/Embedded-Linux/Vivado-2017-1-not-setting-correct-BASEADDR-for-AXI-Bridge-for/m-p/769279#M19963
appended "_pcie" to the names of the KCU105 designs for compatibility with the SDK build script

v2016.4

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KCU105 design: removed CDMA, simplified design, corrected issue with …

…4-lane Gen3 link-up (see notes in the block diagram .tcl file)

v2016.3

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README cleanup

v2016.2

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Set sfp_mgt_clk_sel[1:0] to 10 to route HPC FMC clock as described on…

… page 28 of AC701 user guide UG952

v2016.1

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updated to Vivado 2016.1

removed IP versions and Vivado version check from block diagram tcl

v2015.4

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first commit of PZ 7015-LPC, PZ 7015 and ZC706-HPC designs