Merge pull request pulp-platform#132 from pulp-platform/hotfix/disp-seq

Stall the main controller when changing the `LMUL`

CHANGELOG.md

@@ -29,6 +29,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
  - Fix lane sequencer checks for floating-point comparisons
  - Fix synthesis error occuring due to the continuous assignmnet in the always block of mask unit
  - Fix wrong variable in `vmerge` and `vmv` `riscv-tests`
+ - Re-introduce WAIT_STATE to avoid hazards when changin LMUL
+ - Fix the PEs-ready signals related conditions in the main sequencer
 
 ### Added
 
@@ -52,6 +54,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 - Update LLVM to version `15.0.0` (RVV 1.0)
 - Update Spike to version `1.1.1-dev` (RVV 1.0)
 - Update `newlib` from commit 84d068 to 5192d5
+- Ara's dispatcher goes to WAIT_STATE only when the new LMUL is lower than the old one
 
 ## 2.2.0 - 2021-11-02
 

hardware/src/ara_dispatcher.sv

@@ -124,8 +124,9 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
   // operations, or injecting a reshuffling uop.
   // IDLE can happen, for example, once the vlmul has changed.
   // RESHUFFLE can happen when an instruction writes a register with != EEW
-  typedef enum logic {
+  typedef enum logic [1:0] {
     NORMAL_OPERATION,
+    WAIT_IDLE,
     RESHUFFLE
   } state_e;
   state_e state_d, state_q;
@@ -245,6 +246,11 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
 
     // Special states
     case (state_q)
+      // Is Ara idle?
+      WAIT_IDLE: begin
+        if (ara_idle_i) state_d = NORMAL_OPERATION;
+      end
+
       // Inject a reshuffle instruction
       RESHUFFLE: begin
         // Instruction is of one of the RVV types
@@ -357,6 +363,15 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
 
                 // Return the new vl
                 acc_resp_o.result = vl_d;
+
+                // If the vtype has changed, wait for the backend before issuing any new instructions.
+                // This is to avoid hazards on implicit register labels when LMUL_old > LMUL_new
+                // and both the LMULs are greater then LMUL_1 (i.e., lmul[2] == 1'b0)
+                // Checking only lmul_q is a trick: we want to stall only if both lmuls have
+                // zero MSB. If lmul_q has zero MSB, it's greater than lmul_d only if also
+                // lmul_d has zero MSB since the slice comparison is intrinsically unsigned
+                if (!vtype_q.vlmul[2] && (vtype_d.vlmul[2:0] < vtype_q.vlmul[2:0]))
+                  state_d = WAIT_IDLE;
               end
 
               OPIVV: begin: opivv

hardware/src/ara_sequencer.sv

@@ -424,8 +424,8 @@ module ara_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::i
         pe_req_d       = pe_req_o;
         pe_req_valid_d = pe_req_valid_o;
 
-        // Consume the request if acknowledged
-        if (pe_req_valid_o && pe_req_ready_i)
+        // Consume the request if acknowledged during a scalar move
+        if (pe_req_valid_o && &operand_requester_ready)
           pe_req_valid_d = 1'b0;
 
         // Wait for the address translation
@@ -502,7 +502,7 @@ module ara_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::i
     if (|pe_resp_i[NrLanes+OffsetMask].vinsn_done)
       running_mask_insn_d = 1'b0;
 
-    if (pe_req_valid_o && pe_req_ready_i && pe_req_o.vfu == VFU_MaskUnit)
+    if (pe_req_valid_o && &operand_requester_ready && pe_req_o.vfu == VFU_MaskUnit)
       running_mask_insn_d = 1'b1;
   end