Merge pull request pulp-platform#107 from pulp-platform/hotfix/masku

MASKU hotfixes

CHANGELOG.md

@@ -16,6 +16,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
  - Avoid losing hazard-related information in the pipeline between the main sequencer and the operand requesters
  - Fix anticipated grant bug from operand requester to LDU, SLDU, MASKU, because of the stream registers. Now, the three units wait for a final true grant before commiting
  - The mask unit does not require synchronized lanes anymore to commit an instruction
+ - MASKU does not wait anymore for valid incoming data from inactive lanes
+ - Fix corner-case comparison in MASKU to provide the expected behavior
+ - Fix MaskB-queue vector length in the lane sequencer
 
 ### Added
 

hardware/src/lane/lane_sequencer.sv

@@ -643,8 +643,8 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
             hazard  : pe_req.hazard_vd,
             default : '0
           };
-          if ((pe_req.vl / NrLanes / ELEN) << (int'(EW64) - int'(pe_req.vtype.vsew)) !=
-              pe_req.vl) operand_request_i[MaskB].vl += 1;
+          if (((pe_req.vl / NrLanes / ELEN) * NrLanes * ELEN) !=
+            pe_req.vl) operand_request_i[MaskB].vl += 1;
           operand_request_push[MaskB] = pe_req.use_vd_op;
 
           operand_request_i[MaskM] = '{

hardware/src/masku/masku.sv

@@ -257,7 +257,7 @@ module masku import ara_pkg::*; import rvv_pkg::*; #(
       // from the previous value of the destination register (mask_operand_b_i). Byte strobes
       // do not work here, since this has to be done at a bit granularity. Therefore, the Mask Unit
       // received both operands, and does a masking depending on the value of the vl.
-      if (vinsn_issue.vl > ELEN*NrLanes)
+      if (vinsn_issue.vl >= ELEN*NrLanes)
         bit_enable = '1;
       else begin
         bit_enable[vinsn_issue.vl] = 1'b1;
@@ -386,6 +386,10 @@ module masku import ara_pkg::*; import rvv_pkg::*; #(
   // Remaining elements of the current instruction in the commit phase
   vlen_t commit_cnt_d, commit_cnt_q;
 
+  logic [NrLanes-1:0] fake_a_valid;
+  logic last_incoming_a;
+  logic unbalanced_a;
+
   // Information about which is the target FU of the request
   assign masku_operand_fu = (vinsn_issue.op inside {[VMFEQ:VMFGE]}) ? MaskFUMFpu : MaskFUAlu;
 
@@ -505,13 +509,21 @@ module masku import ara_pkg::*; import rvv_pkg::*; #(
     //  Write results to the lanes  //
     //////////////////////////////////
 
+    assign unbalanced_a = (|commit_cnt_q[idx_width(NrLanes)-1:0] != 1'b0) ? 1'b1 : 1'b0;
+    last_incoming_a = ((commit_cnt_q - vrf_pnt_q) < NrLanes) ? 1'b1 : 1'b0;
+    for (int unsigned i = 1; i < NrLanes; i++)
+      if (i >= {1'b0, commit_cnt_q[idx_width(NrLanes)-1:0]})
+        fake_a_valid[i] = last_incoming_a & unbalanced_a;
+      else
+        fake_a_valid = 1'b0;
+
     // Is there an instruction ready to be issued?
     if (vinsn_issue_valid) begin
       // This instruction executes on the Mask Unit
       if (vinsn_issue.vfu == VFU_MaskUnit) begin
         // Is there place in the result queue to write the results?
         // Did we receive the operands?
-        if (!result_queue_full && &masku_operand_a_valid_i &&
+        if (!result_queue_full && &(masku_operand_a_valid_i | fake_a_valid) &&
             (!vinsn_issue.use_vd_op || &masku_operand_b_valid_i)) begin
           // How many elements are we committing in total?
           // Since we are committing bits instead of bytes, we carry out the following calculation