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XJTUIAIR-CAG

CAG group, Institute of AI & Robitics of Xi'an Jiaotong Univiersity

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  1. XJTU-Tripler XJTU-Tripler Public

    XJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.

    VHDL 175 45

  2. Matterhorn Matterhorn Public

    A novel general neuromorphic computing framework based on PyTorch.

    Python 13 2

  3. Vscale_plus Vscale_plus Public

    A 3-stage in-order single-scalar RISC-V processor

    Verilog 10 3

  4. gem5_dda gem5_dda Public

    A gem5 experimental repo in order to explore Data-dependent Access (DDA).

    C++ 6 4

  5. c910-fpga c910-fpga Public

    An FPGA project of a simple SOC witn Xuantie c906

    TeX 3 2

  6. dmp dmp Public

    Dmp: differential matching prefetcher

    1

Repositories

Showing 7 of 7 repositories
  • Matterhorn Public

    A novel general neuromorphic computing framework based on PyTorch.

    xjtuiair-cag/Matterhorn’s past year of commit activity
    Python 13 MIT-0 2 0 0 Updated Dec 14, 2024
  • gem5_dda Public

    A gem5 experimental repo in order to explore Data-dependent Access (DDA).

    xjtuiair-cag/gem5_dda’s past year of commit activity
    C++ 6 BSD-3-Clause 4 0 0 Updated Jun 5, 2024
  • c910-fpga Public

    An FPGA project of a simple SOC witn Xuantie c906

    xjtuiair-cag/c910-fpga’s past year of commit activity
    TeX 3 2 1 0 Updated May 17, 2024
  • xjtuiair-cag/xjtucag-benchmarks’s past year of commit activity
    Fortran 1 0 0 0 Updated Apr 24, 2024
  • XJTU-Tripler Public

    XJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.

    xjtuiair-cag/XJTU-Tripler’s past year of commit activity
    VHDL 175 45 0 0 Updated Jan 10, 2024
  • dmp Public

    Dmp: differential matching prefetcher

    xjtuiair-cag/dmp’s past year of commit activity
    1 MIT 0 0 0 Updated Dec 22, 2023
  • Vscale_plus Public

    A 3-stage in-order single-scalar RISC-V processor

    xjtuiair-cag/Vscale_plus’s past year of commit activity
    Verilog 10 3 0 0 Updated Oct 24, 2019

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