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Merge pull request sstsimulator#1981 from sstsimulator/devel
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Automatically Merged using SST Master Branch Merger
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@sst-autotester
sst-autotester authored Nov 22, 2022
2 parents 4901692 + d97b45c commit 5a62893
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Showing 73 changed files with 691 additions and 575 deletions.
96 changes: 60 additions & 36 deletions src/sst/elements/vanadis/decoder/vriscv64decoder.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -101,21 +101,28 @@ class VanadisRISCV64Decoder : public VanadisDecoder

void tick(SST::Output* output, uint64_t cycle) override
{
output->verbose(CALL_INFO, 16, 0, "-> Decode step for thr: %" PRIu32 "\n", hw_thr);
output->verbose(CALL_INFO, 16, 0, "---> Max decodes per cycle: %" PRIu16 "\n", max_decodes_per_cycle);
if(output->getVerboseLevel() >= 16) {
output->verbose(CALL_INFO, 16, 0, "-> Decode step for thr: %" PRIu32 "\n", hw_thr);
output->verbose(CALL_INFO, 16, 0, "---> Max decodes per cycle: %" PRIu16 "\n", max_decodes_per_cycle);
}

for ( uint16_t i = 0; i < max_decodes_per_cycle; ++i ) {
if ( !thread_rob->full() ) {
if ( ! thread_rob->full() ) {
if ( ins_loader->hasBundleAt(ip) ) {
// We have the instruction in our micro-op cache
output->verbose(
CALL_INFO, 16, 0, "---> Found uop bundle for ip=0x%llx, loading from cache...\n", ip);
if(output->getVerboseLevel() >= 16) {
output->verbose(
CALL_INFO, 16, 0, "---> Found uop bundle for ip=0x%llx, loading from cache...\n", ip);
}
stat_uop_hit->addData(1);

VanadisInstructionBundle* bundle = ins_loader->getBundleAt(ip);
output->verbose(
CALL_INFO, 16, 0, "----> Bundle contains %" PRIu32 " entries.\n",
bundle->getInstructionCount());

if(output->getVerboseLevel() >= 16) {
output->verbose(
CALL_INFO, 16, 0, "----> Bundle contains %" PRIu32 " entries.\n",
bundle->getInstructionCount());
}

// Do we have enough space in the ROB to push the micro-op bundle into
// the queue?
Expand All @@ -134,11 +141,13 @@ class VanadisRISCV64Decoder : public VanadisDecoder
const uint64_t predicted_address = branch_predictor->predictAddress(ip);
next_spec_ins->setSpeculatedAddress(predicted_address);

output->verbose(
CALL_INFO, 16, 0,
"----> contains a branch: 0x%llx / predicted "
"(found in predictor): 0x%llx\n",
ip, predicted_address);
if(output->getVerboseLevel() >= 16) {
output->verbose(
CALL_INFO, 16, 0,
"----> contains a branch: 0x%llx / predicted "
"(found in predictor): 0x%llx\n",
ip, predicted_address);
}

ip = predicted_address;
bundle_has_branch = true;
Expand All @@ -148,11 +157,13 @@ class VanadisRISCV64Decoder : public VanadisDecoder
// so just speculate that we are going to drop through to the
// next instruction as we aren't sure where this will go yet

output->verbose(
CALL_INFO, 16, 0,
"----> contains a branch: 0x%llx / predicted "
"(not-found in predictor): 0x%llx, pc-increment: %" PRIu64 "\n",
ip, ip + 4, bundle->pcIncrement());
if(output->getVerboseLevel() >= 16) {
output->verbose(
CALL_INFO, 16, 0,
"----> contains a branch: 0x%llx / predicted "
"(not-found in predictor): 0x%llx, pc-increment: %" PRIu64 "\n",
ip, ip + 4, bundle->pcIncrement());
}

ip += bundle->pcIncrement();
next_spec_ins->setSpeculatedAddress(ip);
Expand All @@ -165,10 +176,13 @@ class VanadisRISCV64Decoder : public VanadisDecoder

// Move to the next address, if we had a branch we should have
// already found a predicted target addeess to decode
output->verbose(
CALL_INFO, 16, 0, "----> branch? %s, ip=0x%llx + inc=%" PRIu64 " = new-ip=0x%llx\n",
bundle_has_branch ? "yes" : "no", ip, bundle_has_branch ? 0 : bundle->pcIncrement(),
bundle_has_branch ? ip : ip + bundle->pcIncrement());
if(output->getVerboseLevel() >= 16) {
output->verbose(
CALL_INFO, 16, 0, "----> branch? %s, ip=0x%llx + inc=%" PRIu64 " = new-ip=0x%llx\n",
bundle_has_branch ? "yes" : "no", ip, bundle_has_branch ? 0 : bundle->pcIncrement(),
bundle_has_branch ? ip : ip + bundle->pcIncrement());
}

ip = bundle_has_branch ? ip : ip + bundle->pcIncrement();
}
else {
Expand All @@ -179,11 +193,14 @@ class VanadisRISCV64Decoder : public VanadisDecoder
}
else if ( ins_loader->hasPredecodeAt(ip, 4) ) {
// We have a loaded instruction cache line but have not decoded it yet
output->verbose(
CALL_INFO, 16, 0,
"---> uop not found, but is located in the predecode "
"i0-icache (ip=0x%llx)\n",
ip);
if(output->getVerboseLevel() >= 16) {
output->verbose(
CALL_INFO, 16, 0,
"---> uop not found, but is located in the predecode "
"i0-icache (ip=0x%llx)\n",
ip);
}

VanadisInstructionBundle* decoded_bundle = new VanadisInstructionBundle(ip);
stat_predecode_hit->addData(1);

Expand All @@ -196,9 +213,11 @@ class VanadisRISCV64Decoder : public VanadisDecoder
output->verbose(CALL_INFO, 16, 0, "---> performing a decode for ip=0x%llx\n", ip);
decode(output, ip, temp_ins, decoded_bundle);

output->verbose(
CALL_INFO, 16, 0, "---> bundle generates %" PRIu32 " micro-ops\n",
(uint32_t)decoded_bundle->getInstructionCount());
if(output->getVerboseLevel() >= 16) {
output->verbose(
CALL_INFO, 16, 0, "---> bundle generates %" PRIu32 " micro-ops\n",
(uint32_t)decoded_bundle->getInstructionCount());
}

ins_loader->cacheDecodedBundle(decoded_bundle);

Expand All @@ -221,11 +240,13 @@ class VanadisRISCV64Decoder : public VanadisDecoder
else {
// Not in micro or predecode cache, so we have to regenrata a request
// and stop further processing
output->verbose(
CALL_INFO, 16, 0,
"---> microop bundle and pre-decoded bytes are not found for "
"0x%llx, requested read for cache line (line=%" PRIu64 ")\n",
ip, ins_loader->getCacheLineWidth());
if(output->getVerboseLevel() >= 16) {
output->verbose(
CALL_INFO, 16, 0,
"---> microop bundle and pre-decoded bytes are not found for "
"0x%llx, requested read for cache line (line=%" PRIu64 ")\n",
ip, ins_loader->getCacheLineWidth());
}
ins_loader->requestLoadAt(output, ip, 4);
stat_ins_bytes_loaded->addData(4);
stat_predecode_miss->addData(1);
Expand All @@ -237,10 +258,13 @@ class VanadisRISCV64Decoder : public VanadisDecoder
CALL_INFO, 16, 0,
"---> Decode pending queue (ROB) is full, no more "
"decoded permitted this cycle.\n");
break;
}
}

output->verbose(CALL_INFO, 16, 0, "---> cycle is completed, ip=0x%llx\n", ip);
if(output->getVerboseLevel() >= 16) {
output->verbose(CALL_INFO, 16, 0, "---> cycle is completed, ip=0x%llx\n", ip);
}
}

protected:
Expand Down
66 changes: 47 additions & 19 deletions src/sst/elements/vanadis/inst/regstack.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -22,54 +22,82 @@ namespace Vanadis {
class VanadisRegisterStack
{
public:
VanadisRegisterStack(const size_t count) : reg_count(count), max_capacity(count)
VanadisRegisterStack(const size_t count) : max_capacity(count)
{
regs.reserve(count);

for(auto i = 0; i < count; ++i) {
regs.push_back(i);
}
regs = new uint16_t[max_capacity];
reset();
}

~VanadisRegisterStack() {}
~VanadisRegisterStack() {
delete[] regs;
}

uint16_t pop()
{
uint16_t temp = regs.back();
regs.pop_back();
/*
if(stack_top < 0) {
printf("LOGIC-ERROR - stack_top=%" PRId32 " / capacity=%" PRId32 "\n", stack_top, max_capacity);
int32_t* address = 0;
*address = 0;
printf("address=%" PRId32 "\n", *address);
}
assert(stack_top >= 0);
*/
const uint16_t temp = regs[stack_top];
stack_top--;
return temp;
}

void push(const uint16_t v)
{
regs.push_back(v);
/*
if(stack_top >= max_capacity) {
printf("LOGIC-ERROR - stack_top=%" PRId32 " / capacity=%" PRId32 "\n", stack_top, max_capacity);
int32_t* address = 0;
*address = 0;
printf("address=%" PRId32 "\n", *address);
} else {
printf("-> stack_top=%" PRId32 " / capacity=%" PRId32 "\n", stack_top, max_capacity);
}
assert(stack_top < max_capacity);
*/
stack_top++;
regs[stack_top] = v;
}

size_t capacity() const { return max_capacity; }
size_t unused() const { return (stack_top > 0) ? stack_top : 0; }

size_t unused() const { return size(); }
bool full() { return (stack_top == (max_capacity - 1)); }
bool empty() { return -1 == stack_top; }

size_t size() const { return regs.size(); }
void clear() {
stack_top = -1;
}

bool full() { return (0 == size()); }
bool empty() { return size() == capacity(); }
void reset() {
stack_top = max_capacity - 1;

void clear() { regs.clear(); }
for(auto i = 0; i < max_capacity; ++i) {
regs[i] = i;
}
}

void print() {
printf("----> free registers = { ");

for(size_t i = 0; i < regs.size(); ++i) {
for(size_t i = 0; i < stack_top; ++i) {
printf("%" PRIu16 ", ", regs[i]);
}

printf("}\n");
}

private:
size_t max_capacity;
size_t reg_count;
std::vector<uint16_t> regs;
const int32_t max_capacity;
int32_t stack_top;

uint16_t* regs;
};

} // namespace Vanadis
Expand Down
14 changes: 8 additions & 6 deletions src/sst/elements/vanadis/inst/vadd.h
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Original file line number Diff line number Diff line change
Expand Up @@ -60,12 +60,14 @@ class VanadisAddInstruction : public VanadisInstruction
void execute(SST::Output* output, VanadisRegisterFile* regFile) override
{
#ifdef VANADIS_BUILD_DEBUG
output->verbose(
CALL_INFO, 16, 0,
"Execute: 0x%llx %s phys: out=%" PRIu16 " in=%" PRIu16 ", %" PRIu16 ", isa: out=%" PRIu16
" / in=%" PRIu16 ", %" PRIu16 "\n",
getInstructionAddress(), getInstCode(), phys_int_regs_out[0], phys_int_regs_in[0],
phys_int_regs_in[1], isa_int_regs_out[0], isa_int_regs_in[0], isa_int_regs_in[1]);
if(output->getVerboseLevel() >= 16) {
output->verbose(
CALL_INFO, 16, 0,
"Execute: 0x%llx %s phys: out=%" PRIu16 " in=%" PRIu16 ", %" PRIu16 ", isa: out=%" PRIu16
" / in=%" PRIu16 ", %" PRIu16 "\n",
getInstructionAddress(), getInstCode(), phys_int_regs_out[0], phys_int_regs_in[0],
phys_int_regs_in[1], isa_int_regs_out[0], isa_int_regs_in[0], isa_int_regs_in[1]);
}
#endif

const gpr_format src_1 = regFile->getIntReg<gpr_format>(phys_int_regs_in[0]);
Expand Down
30 changes: 16 additions & 14 deletions src/sst/elements/vanadis/inst/vaddi.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -69,20 +69,22 @@ class VanadisAddImmInstruction : public VanadisInstruction
const gpr_format result = src_1 + imm_value;

#ifdef VANADIS_BUILD_DEBUG
if(std::is_unsigned<gpr_format>::value) {
output->verbose(
CALL_INFO, 16, 0,
"Execute: 0x%llx %s phys: out=%" PRIu16 " in=%" PRIu16 " imm=%" PRId64 ", isa: out=%" PRIu16
" / in=%" PRIu16 " (%" PRIu64 " + %" PRIu64 " = %" PRIu64 ")\n",
getInstructionAddress(), getInstCode(), phys_int_regs_out[0], phys_int_regs_in[0], imm_value, isa_int_regs_out[0],
isa_int_regs_in[0], src_1, imm_value, result);
} else {
output->verbose(
CALL_INFO, 16, 0,
"Execute: 0x%llx %s phys: out=%" PRIu16 " in=%" PRIu16 " imm=%" PRId64 ", isa: out=%" PRIu16
" / in=%" PRIu16 " (%" PRId64 " + %" PRId64 " = %" PRId64 ")\n",
getInstructionAddress(), getInstCode(), phys_int_regs_out[0], phys_int_regs_in[0], imm_value, isa_int_regs_out[0],
isa_int_regs_in[0], src_1, imm_value, result);
if(output->getVerboseLevel() >= 16) {
if(std::is_unsigned<gpr_format>::value) {
output->verbose(
CALL_INFO, 16, 0,
"Execute: 0x%llx %s phys: out=%" PRIu16 " in=%" PRIu16 " imm=%" PRId64 ", isa: out=%" PRIu16
" / in=%" PRIu16 " (%" PRIu64 " + %" PRIu64 " = %" PRIu64 ")\n",
getInstructionAddress(), getInstCode(), phys_int_regs_out[0], phys_int_regs_in[0], imm_value, isa_int_regs_out[0],
isa_int_regs_in[0], src_1, imm_value, result);
} else {
output->verbose(
CALL_INFO, 16, 0,
"Execute: 0x%llx %s phys: out=%" PRIu16 " in=%" PRIu16 " imm=%" PRId64 ", isa: out=%" PRIu16
" / in=%" PRIu16 " (%" PRId64 " + %" PRId64 " = %" PRId64 ")\n",
getInstructionAddress(), getInstCode(), phys_int_regs_out[0], phys_int_regs_in[0], imm_value, isa_int_regs_out[0],
isa_int_regs_in[0], src_1, imm_value, result);
}
}
#endif

Expand Down
14 changes: 8 additions & 6 deletions src/sst/elements/vanadis/inst/vaddiu.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -52,12 +52,14 @@ class VanadisAddImmUnsignedInstruction : public VanadisInstruction
void execute(SST::Output* output, VanadisRegisterFile* regFile) override
{
#ifdef VANADIS_BUILD_DEBUG
output->verbose(
CALL_INFO, 16, 0,
"Execute: (addr=%p) ADDIU phys: out=%" PRIu16 " in=%" PRIu16 " imm=%" PRId64 ", isa: out=%" PRIu16
" / in=%" PRIu16 "\n",
(void*)getInstructionAddress(), phys_int_regs_out[0], phys_int_regs_in[0], imm_value, isa_int_regs_out[0],
isa_int_regs_in[0]);
if(output->getVerboseLevel() >= 16) {
output->verbose(
CALL_INFO, 16, 0,
"Execute: (addr=%p) ADDIU phys: out=%" PRIu16 " in=%" PRIu16 " imm=%" PRId64 ", isa: out=%" PRIu16
" / in=%" PRIu16 "\n",
(void*)getInstructionAddress(), phys_int_regs_out[0], phys_int_regs_in[0], imm_value, isa_int_regs_out[0],
isa_int_regs_in[0]);
}
#endif

if ( VanadisRegisterFormat::VANADIS_FORMAT_INT64 == register_format ) {
Expand Down
14 changes: 8 additions & 6 deletions src/sst/elements/vanadis/inst/vand.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -51,12 +51,14 @@ class VanadisAndInstruction : public VanadisInstruction
void execute(SST::Output* output, VanadisRegisterFile* regFile) override
{
#ifdef VANADIS_BUILD_DEBUG
output->verbose(
CALL_INFO, 16, 0,
"Execute: (addr=%p) AND phys: out=%" PRIu16 " in=%" PRIu16 ", %" PRIu16 ", isa: out=%" PRIu16
" / in=%" PRIu16 ", %" PRIu16 "\n",
(void*)getInstructionAddress(), phys_int_regs_out[0], phys_int_regs_in[0], phys_int_regs_in[1],
isa_int_regs_out[0], isa_int_regs_in[0], isa_int_regs_in[1]);
if(output->getVerboseLevel() >= 16) {
output->verbose(
CALL_INFO, 16, 0,
"Execute: (addr=%p) AND phys: out=%" PRIu16 " in=%" PRIu16 ", %" PRIu16 ", isa: out=%" PRIu16
" / in=%" PRIu16 ", %" PRIu16 "\n",
(void*)getInstructionAddress(), phys_int_regs_out[0], phys_int_regs_in[0], phys_int_regs_in[1],
isa_int_regs_out[0], isa_int_regs_in[0], isa_int_regs_in[1]);
}
#endif
const uint64_t src_1 = regFile->getIntReg<uint64_t>(phys_int_regs_in[0]);
const uint64_t src_2 = regFile->getIntReg<uint64_t>(phys_int_regs_in[1]);
Expand Down
14 changes: 8 additions & 6 deletions src/sst/elements/vanadis/inst/vandi.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -50,12 +50,14 @@ class VanadisAndImmInstruction : public VanadisInstruction
void execute(SST::Output* output, VanadisRegisterFile* regFile) override
{
#ifdef VANADIS_BUILD_DEBUG
output->verbose(
CALL_INFO, 16, 0,
"Execute: (addr=%p) ANDI phys: out=%" PRIu16 " in=%" PRIu16 " imm=%" PRIu64 ", isa: out=%" PRIu16
" / in=%" PRIu16 "\n",
(void*)getInstructionAddress(), phys_int_regs_out[0], phys_int_regs_in[0], imm_value, isa_int_regs_out[0],
isa_int_regs_in[0]);
if(output->getVerboseLevel() >= 16) {
output->verbose(
CALL_INFO, 16, 0,
"Execute: (addr=%p) ANDI phys: out=%" PRIu16 " in=%" PRIu16 " imm=%" PRIu64 ", isa: out=%" PRIu16
" / in=%" PRIu16 "\n",
(void*)getInstructionAddress(), phys_int_regs_out[0], phys_int_regs_in[0], imm_value, isa_int_regs_out[0],
isa_int_regs_in[0]);
}
#endif
const uint64_t src_1 = regFile->getIntReg<uint64_t>(phys_int_regs_in[0]);
regFile->setIntReg<uint64_t>(phys_int_regs_out[0], (src_1 & imm_value));
Expand Down
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