AXI, AXI stream, Ethernet, and PCIe components in System Verilog

A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

A minimal GPU design in Verilog to learn how GPUs work from the ground up

Wrapped, but for Weekly Reports

Yosys Open SYnthesis Suite

Input / Output Physical Memory Protection Unit for RISC-V

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

A matrix extension proposal for AI applications under RISC-V architecture

Simple runtime for Pulp platforms