Fix lines that have incorrect indentation or exceed 80 columns. There…

… is no change in functionality.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129606 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Mips/Makefile

@@ -1,11 +1,11 @@
-##===- lib/Target/Mips/Makefile ----------------------------*- Makefile -*-===##
+##===- lib/Target/Mips/Makefile ---------------------------*- Makefile -*-===##
 #
 #                     The LLVM Compiler Infrastructure
 #
 # This file is distributed under the University of Illinois Open Source
 # License. See LICENSE.TXT for details.
 #
-##===----------------------------------------------------------------------===##
+##===---------------------------------------------------------------------===##
 
 LEVEL = ../../..
 LIBRARYNAME = LLVMMipsCodeGen

lib/Target/Mips/Mips.h

@@ -1,16 +1,16 @@
-//===-- Mips.h - Top-level interface for Mips representation ----*- C++ -*-===//
+//===-- Mips.h - Top-level interface for Mips representation ---*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 //
 // This file contains the entry points for global functions defined in
 // the LLVM Mips back-end.
 //
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 
 #ifndef TARGET_MIPS_H
 #define TARGET_MIPS_H

lib/Target/Mips/Mips.td

@@ -1,23 +1,23 @@
-//===- Mips.td - Describe the Mips Target Machine ----------*- tablegen -*-===//
+//===- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 // This is the top level entry point for the Mips target.
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 // Target-independent interfaces
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 
 include "llvm/Target/Target.td"
 
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 // Register File, Calling Conv, Instruction Descriptions
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 
 include "MipsRegisterInfo.td"
 include "MipsSchedule.td"
@@ -26,16 +26,17 @@ include "MipsCallingConv.td"
 
 def MipsInstrInfo : InstrInfo;
 
-//===----------------------------------------------------------------------===//
-// Mips Subtarget features                                                    //
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
+// Mips Subtarget features                                                   //
+//===---------------------------------------------------------------------===//
 
 def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
                                 "General Purpose Registers are 64-bit wide.">;
 def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
                                 "Support 64-bit FP registers.">;
 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
-                                "true", "Only supports single precision float">;
+                                "true",
+                                "Only supports single precision float">;
 def FeatureO32         : SubtargetFeature<"o32", "MipsABI", "O32",
                                 "Enable o32 ABI">;
 def FeatureEABI        : SubtargetFeature<"eabi", "MipsABI", "EABI",
@@ -58,16 +59,16 @@ def FeatureMips1       : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
                                 "Mips1 ISA Support">;
 def FeatureMips2       : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
                                 "Mips2 ISA Support">;
-def FeatureMips32      : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
-                                "Mips32 ISA Support",
+def FeatureMips32      : SubtargetFeature<"mips32", "MipsArchVersion",
+                                "Mips32", "Mips32 ISA Support",
                                 [FeatureCondMov, FeatureBitCount]>;
 def FeatureMips32r2    : SubtargetFeature<"mips32r2", "MipsArchVersion",
                                 "Mips32r2", "Mips32r2 ISA Support",
                                 [FeatureMips32, FeatureSEInReg]>;
 
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 // Mips processors supported.
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 
 class Proc<string Name, list<SubtargetFeature> Features>
  : Processor<Name, MipsGenericItineraries, Features>;

lib/Target/Mips/MipsAsmPrinter.cpp

@@ -1,16 +1,16 @@
-//===-- MipsAsmPrinter.cpp - Mips LLVM assembly writer --------------------===//
+//===-- MipsAsmPrinter.cpp - Mips LLVM assembly writer -------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 //
 // This file contains a printer that converts from our internal representation
 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
 //
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 
 #define DEBUG_TYPE "mips-asm-printer"
 #include "Mips.h"
@@ -68,7 +68,8 @@ namespace {
     const char *getCurrentABIString() const;
     void emitFrameDirective();
 
-    void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen'd.
+    void printInstruction(const MachineInstr *MI,
+                          raw_ostream &O); // autogen'd.
     void EmitInstruction(const MachineInstr *MI) {
       SmallString<128> Str;
       raw_svector_ostream OS(Str);
@@ -77,7 +78,8 @@ namespace {
     }
     virtual void EmitFunctionBodyStart();
     virtual void EmitFunctionBodyEnd();
-    virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const;
+    virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock
+                                                   *MBB) const;
     static const char *getRegisterName(unsigned RegNo);
 
     virtual void EmitFunctionEntryLabel();
@@ -87,7 +89,7 @@ namespace {
 
 #include "MipsGenAsmWriter.inc"
 
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 //
 //  Mips Asm Directives
 //
@@ -116,11 +118,11 @@ namespace {
 //    stack pointer subtration, the first register in the mask (RA) will be
 //    saved at address 48-8=40.
 //
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 // Mask directives
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 
 // Create a bitmask with all callee saved registers for CPU or Floating Point
 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
@@ -172,9 +174,9 @@ void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) {
     O << utohexstr((Value & (0xF << (i*4))) >> (i*4));
 }
 
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 // Frame and Set directives
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 
 /// Frame Directive
 void MipsAsmPrinter::emitFrameDirective() {
@@ -236,8 +238,8 @@ void MipsAsmPrinter::EmitFunctionBodyEnd() {
 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
 /// exactly one predecessor and the control transfer mechanism between
 /// the predecessor and this block is a fall-through.
-bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB)
-    const {
+bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock
+                                                       *MBB) const {
   // The predecessor has to be immediately before this block.
   const MachineBasicBlock *Pred = *MBB->pred_begin();
 
@@ -390,7 +392,8 @@ void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
   // FIXME: Use SwitchSection.
 
   // Tell the assembler which ABI we are using
-  OutStreamer.EmitRawText("\t.section .mdebug." + Twine(getCurrentABIString()));
+  OutStreamer.EmitRawText("\t.section .mdebug." +
+                          Twine(getCurrentABIString()));
 
   // TODO: handle O64 ABI
   if (Subtarget->isABI_EABI()) {

lib/Target/Mips/MipsCallingConv.td

@@ -1,21 +1,21 @@
-//===- MipsCallingConv.td - Calling Conventions for Mips ---*- tablegen -*-===//
+//===- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 // This describes the calling conventions for Mips architecture.
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 
 /// CCIfSubtarget - Match if the current subtarget has a feature F.
 class CCIfSubtarget<string F, CCAction A>:
   CCIf<!strconcat("State.getTarget().getSubtarget<MipsSubtarget>().", F), A>;
 
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 // Mips O32 Calling Convention
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 
 // Only the return rules are defined here for O32. The rules for argument
 // passing are defined in MipsISelLowering.cpp.
@@ -30,9 +30,9 @@ def RetCC_MipsO32 : CallingConv<[
   CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0, D1]>>>
 ]>;
 
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 // Mips EABI Calling Convention
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 
 def CC_MipsEABI : CallingConv<[
   // Promote i8/i16 arguments to i32.
@@ -72,9 +72,9 @@ def RetCC_MipsEABI : CallingConv<[
   CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0]>>>
 ]>;
 
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 // Mips Calling Convention Dispatch
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 
 def CC_Mips : CallingConv<[
   CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>

lib/Target/Mips/MipsDelaySlotFiller.cpp

@@ -5,11 +5,11 @@
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 //
 // Simple pass to fills delay slots with NOPs.
 //
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 
 #define DEBUG_TYPE "delay-slot-filler"
 

lib/Target/Mips/MipsExpandPseudo.cpp

@@ -1,16 +1,16 @@
-//===--  MipsExpandPseudo.cpp - Expand pseudo instructions ---------------------===//
+//===--  MipsExpandPseudo.cpp - Expand pseudo instructions ---------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 //
-// This pass expands pseudo instructions into target instructions after register
-// allocation but before post-RA scheduling.
+// This pass expands pseudo instructions into target instructions after
+// register allocation but before post-RA scheduling.
 //
-//===----------------------------------------------------------------------===//
+//===---------------------------------------------------------------------===//
 
 #define DEBUG_TYPE "mips-expand-pseudo"
 
@@ -42,7 +42,8 @@ namespace {
 
   private:
     void ExpandBuildPairF64(MachineBasicBlock&, MachineBasicBlock::iterator);
-    void ExpandExtractElementF64(MachineBasicBlock&, MachineBasicBlock::iterator);
+    void ExpandExtractElementF64(MachineBasicBlock&,
+                                 MachineBasicBlock::iterator);
   };
   char MipsExpandPseudo::ID = 0;
 } // end of anonymous namespace
@@ -85,7 +86,8 @@ bool MipsExpandPseudo::runOnMachineBasicBlock(MachineBasicBlock& MBB) {
 void MipsExpandPseudo::ExpandBuildPairF64(MachineBasicBlock& MBB,
                                             MachineBasicBlock::iterator I) {  
   unsigned DstReg = I->getOperand(0).getReg();
-  unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
+  unsigned LoReg = I->getOperand(1).getReg();
+  unsigned HiReg = I->getOperand(2).getReg();
   const TargetInstrDesc& Mtc1Tdd = TII->get(Mips::MTC1);
   DebugLoc dl = I->getDebugLoc();
   const unsigned* SubReg =
@@ -98,7 +100,7 @@ void MipsExpandPseudo::ExpandBuildPairF64(MachineBasicBlock& MBB,
 }
 
 void MipsExpandPseudo::ExpandExtractElementF64(MachineBasicBlock& MBB,
-                                                 MachineBasicBlock::iterator I) {
+                                               MachineBasicBlock::iterator I) {
   unsigned DstReg = I->getOperand(0).getReg();
   unsigned SrcReg = I->getOperand(1).getReg();
   unsigned N = I->getOperand(2).getImm();