[AVR] XFAIL a set of failing CodeGen tests

There are about 3 underlying bugs causing the tests to fail. On top of that, some tests just we're 'generic' enough. i.e. 32-bit registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294434 91177308-0d34-0410-b5e6-96231b3b80d8
yws · Feb 8, 2017 · f5cac02 · f5cac02
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diff --git a/test/CodeGen/Generic/2003-07-29-BadConstSbyte.ll b/test/CodeGen/Generic/2003-07-29-BadConstSbyte.ll
@@ -1,5 +1,8 @@
 ; RUN: llc < %s
 
+; Bug: PR31341
+; XFAIL: avr
+
 ;; Date:     Jul 29, 2003.
 ;; From:     test/Programs/MultiSource/Ptrdist-bc
 ;; Function: ---

diff --git a/test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll b/test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll
@@ -3,6 +3,9 @@
 ; PR1308
 ; PR1557
 
+; Bug: PR31336
+; XFAIL: avr
+
 define i32 @stuff(i32, ...) {
         %foo = alloca i8*
         %bar = alloca i32*

diff --git a/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll b/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll
@@ -1,5 +1,7 @@
 ; RUN: llc -no-integrated-as < %s
 
+; XFAIL: avr
+
 define fastcc void @bc__support__high_resolution_time__initialize_clock_rate() personality i32 (...)* @__gxx_personality_v0 {
 entry:
   invoke void asm "rdtsc\0A\09movl %eax, $0\0A\09movl %edx, $1", "=*imr,=*imr,~{dirflag},~{fpsr},~{flags},~{dx},~{ax}"( i32* null, i32* null )

diff --git a/test/CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll b/test/CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll
@@ -1,4 +1,8 @@
 ; RUN: llc < %s
+
+; Bug: PR31898
+; XFAIL: avr
+
 ; This caused ScheduleDAG to crash in EmitPhysRegCopy when searching
 ; the uses of a copy to a physical register without ignoring non-data
 ; dependence, PR10220.

diff --git a/test/CodeGen/Generic/MachineBranchProb.ll b/test/CodeGen/Generic/MachineBranchProb.ll
@@ -7,6 +7,9 @@
 ; to fail.
 ; XFAIL: hexagon
 
+; Bug: PR31899
+; XFAIL: avr
+
 ; Make sure we have the correct weight attached to each successor.
 define i32 @test2(i32 %x) nounwind uwtable readnone ssp {
 ; CHECK-LABEL: Machine code for function test2:

diff --git a/test/CodeGen/Generic/inline-asm-mem-clobber.ll b/test/CodeGen/Generic/inline-asm-mem-clobber.ll
@@ -1,5 +1,8 @@
 ; RUN: llc -O2 -no-integrated-as < %s | FileCheck %s
 
+; Test uses 32-bit registers which aren't supported on AVR.
+; XFAIL: avr
+
 @G = common global i32 0, align 4
 
 define i32 @foo(i8* %p) nounwind uwtable {

diff --git a/test/CodeGen/Generic/select-cc.ll b/test/CodeGen/Generic/select-cc.ll
@@ -1,6 +1,11 @@
 ; RUN: llc < %s
+
 ; PR2504
 ; XFAIL: hexagon
+
+; PR31338
+; XFAIL: avr
+
 define <2 x double> @vector_select(<2 x double> %x, <2 x double> %y) nounwind  {
 	%x.lo = extractelement <2 x double> %x, i32 0		; <double> [#uses=1]
 	%x.lo.ge = fcmp oge double %x.lo, 0.000000e+00		; <i1> [#uses=1]

diff --git a/test/CodeGen/Generic/v-split.ll b/test/CodeGen/Generic/v-split.ll
@@ -1,4 +1,8 @@
 ; RUN: llc < %s
+
+; Bug: PR31898
+; XFAIL: avr
+
 %f8 = type <8 x float>
 
 define void @test_f8(%f8 *%P, %f8* %Q, %f8 *%S) {

diff --git a/test/CodeGen/Generic/vector-redux.ll b/test/CodeGen/Generic/vector-redux.ll
@@ -1,6 +1,9 @@
 ; RUN: llc < %s -debug-only=isel -o /dev/null 2>&1 | FileCheck %s
 ; REQUIRES: asserts
 
+; Bug: PR31898
+; XFAIL: avr
+
 @a = global [1024 x i32] zeroinitializer, align 16
 
 define i32 @reduce_add() {

diff --git a/test/CodeGen/Generic/vector.ll b/test/CodeGen/Generic/vector.ll
@@ -1,6 +1,9 @@
 ; Test that vectors are scalarized/lowered correctly.
 ; RUN: llc < %s
 
+; Bug: PR31898
+; XFAIL: avr
+
 %d8 = type <8 x double>
 %f1 = type <1 x float>
 %f2 = type <2 x float>