Research paper based on or related to ABC.

C++ logic network library

Showcase examples for EPFL logic synthesis libraries

Github Pages template for academic personal websites, forked from mmistakes/minimal-mistakes

[SIGIR'2024] "GraphGPT: Graph Instruction Tuning for Large Language Models"

OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

Python-based Hardware Design Processing Toolkit for Verilog HDL

QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification

Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)

The AI Scientist: Towards Fully Automated Open-Ended Scientific Discovery 🧑‍🔬

LLM4HWDesign Starting Toolkit

This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".

Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)

Must-read Papers on Large Language Model (LLM) as Optimizers and Automatic Optimization for Prompting LLMs.

Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)

🔥 Linux下C++轻量级WebServer服务器

2018 ICCAD CONTEST ProblemA Smart EC : Program-Building for Name Mapping. Team cada039.

2018 ICCAD contest problem A ｢Smart EC: Program-Building for Name Mapping｣

Reads a state transition system and performs property checking

Modular hardware build system

涵盖C++ Primer 5th、 effective C++ 、 STL api和demos C++ 基础知识与理论、 智能指针、C++11、 Git教程 Linux命令 Unix操作系统（进程、线程、内存管理、信号）计算机网络、 数据结构（排序、查找）、数据库、、C++对象模型、 设计模式、算法（《剑指offer》、leetcode、lintcode、hihocoder、《王道程序员求职…

ABC: System for Sequential Logic Synthesis and Formal Verification

AIGER And-Inverter-Graph Library