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Merge pull request chipsalliance#2196 from chipsalliance/vector-0.8
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Incorporate some V extension 0.8 changes
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@aswaterman
aswaterman authored Nov 26, 2019
2 parents 2a8432d + bc257f1 commit 2b04884
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Showing 2 changed files with 31 additions and 28 deletions.
11 changes: 6 additions & 5 deletions src/main/scala/rocket/CSR.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -258,8 +258,8 @@ object VType {

def fromUInt(that: UInt)(implicit p: Parameters): VType = fromUInt(that, false)

def computeVL(avl: UInt, vtype: UInt, currentVL: UInt, useCurrentVL: Bool, useZero: Bool)(implicit p: Parameters): UInt =
VType.fromUInt(vtype, true).vl(avl, currentVL, useCurrentVL, useZero)
def computeVL(avl: UInt, vtype: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool)(implicit p: Parameters): UInt =
VType.fromUInt(vtype, true).vl(avl, currentVL, useCurrentVL, useMax, useZero)
}

class VType(implicit p: Parameters) extends CoreBundle {
Expand All @@ -274,8 +274,8 @@ class VType(implicit p: Parameters) extends CoreBundle {
def vlMax: UInt = (maxVLMax >> (this.vsew +& ~this.vlmul)).andNot(minVLMax-1)
def vlMaxInBytes: UInt = maxVLMax >> ~this.vlmul

def vl(avl: UInt, currentVL: UInt, useCurrentVL: Bool, useZero: Bool): UInt = {
val atLeastMaxVLMax = Mux(useCurrentVL, currentVL >= maxVLMax, avl >= maxVLMax)
def vl(avl: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool): UInt = {
val atLeastMaxVLMax = useMax || Mux(useCurrentVL, currentVL >= maxVLMax, avl >= maxVLMax)
val avl_lsbs = Mux(useCurrentVL, currentVL, avl)(maxVLMax.log2 - 1, 0)

val atLeastVLMax = atLeastMaxVLMax || (avl_lsbs & (-maxVLMax.S >> (this.vsew +& ~this.vlmul)).asUInt.andNot(minVLMax-1)).orR
Expand Down Expand Up @@ -477,7 +477,8 @@ class CSRFile(
val vector_csrs = if (!usingVector) LinkedHashMap() else LinkedHashMap[Int,Bits](
CSRs.vstart -> reg_vstart.get,
CSRs.vtype -> reg_vconfig.get.vtype.asUInt,
CSRs.vl -> reg_vconfig.get.vl)
CSRs.vl -> reg_vconfig.get.vl,
CSRs.vlenb -> (vLen / 8).U)

read_mapping ++= debug_csrs
read_mapping ++= fp_csrs
Expand Down
48 changes: 25 additions & 23 deletions src/main/scala/rocket/Instructions.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -294,6 +294,8 @@ object Instructions {
def VSH_V = BitPat("b???000?00000?????101?????0100111")
def VSW_V = BitPat("b???000?00000?????110?????0100111")
def VSE_V = BitPat("b???000?00000?????111?????0100111")
def VL1R_V = BitPat("b000000101000?????111?????0000111")
def VS1R_V = BitPat("b000000101000?????111?????0100111")
def VLSB_V = BitPat("b???110???????????000?????0000111")
def VLSH_V = BitPat("b???110???????????101?????0000111")
def VLSW_V = BitPat("b???110???????????110?????0000111")
Expand Down Expand Up @@ -432,10 +434,10 @@ object Instructions {
def VRGATHER_VX = BitPat("b001100???????????100?????1010111")
def VSLIDEUP_VX = BitPat("b001110???????????100?????1010111")
def VSLIDEDOWN_VX = BitPat("b001111???????????100?????1010111")
def VADC_VXM = BitPat("b0100001??????????100?????1010111")
def VMADC_VXM = BitPat("b0100011??????????100?????1010111")
def VSBC_VXM = BitPat("b0100101??????????100?????1010111")
def VMSBC_VXM = BitPat("b0100111??????????100?????1010111")
def VADC_VXM = BitPat("b0100000??????????100?????1010111")
def VMADC_VXM = BitPat("b010001???????????100?????1010111")
def VSBC_VXM = BitPat("b0100100??????????100?????1010111")
def VMSBC_VXM = BitPat("b010011???????????100?????1010111")
def VMERGE_VXM = BitPat("b0101110??????????100?????1010111")
def VMV_V_X = BitPat("b010111100000?????100?????1010111")
def VMSEQ_VX = BitPat("b011000???????????100?????1010111")
Expand All @@ -450,9 +452,7 @@ object Instructions {
def VSADD_VX = BitPat("b100001???????????100?????1010111")
def VSSUBU_VX = BitPat("b100010???????????100?????1010111")
def VSSUB_VX = BitPat("b100011???????????100?????1010111")
def VAADD_VX = BitPat("b100100???????????100?????1010111")
def VSLL_VX = BitPat("b100101???????????100?????1010111")
def VASUB_VX = BitPat("b100110???????????100?????1010111")
def VSMUL_VX = BitPat("b100111???????????100?????1010111")
def VSRL_VX = BitPat("b101000???????????100?????1010111")
def VSRA_VX = BitPat("b101001???????????100?????1010111")
Expand All @@ -462,10 +462,6 @@ object Instructions {
def VNSRA_VX = BitPat("b101101???????????100?????1010111")
def VNCLIPU_VX = BitPat("b101110???????????100?????1010111")
def VNCLIP_VX = BitPat("b101111???????????100?????1010111")
def VWSMACCU_VX = BitPat("b111100???????????100?????1010111")
def VWSMACC_VX = BitPat("b111101???????????100?????1010111")
def VWSMACCUS_VX = BitPat("b111110???????????100?????1010111")
def VWSMACCSU_VX = BitPat("b111111???????????100?????1010111")
def VADD_VV = BitPat("b000000???????????000?????1010111")
def VSUB_VV = BitPat("b000010???????????000?????1010111")
def VMINU_VV = BitPat("b000100???????????000?????1010111")
Expand All @@ -476,10 +472,10 @@ object Instructions {
def VOR_VV = BitPat("b001010???????????000?????1010111")
def VXOR_VV = BitPat("b001011???????????000?????1010111")
def VRGATHER_VV = BitPat("b001100???????????000?????1010111")
def VADC_VVM = BitPat("b0100001??????????000?????1010111")
def VMADC_VVM = BitPat("b0100011??????????000?????1010111")
def VSBC_VVM = BitPat("b0100101??????????000?????1010111")
def VMSBC_VVM = BitPat("b0100111??????????000?????1010111")
def VADC_VVM = BitPat("b0100000??????????000?????1010111")
def VMADC_VVM = BitPat("b010001???????????000?????1010111")
def VSBC_VVM = BitPat("b0100100??????????000?????1010111")
def VMSBC_VVM = BitPat("b010011???????????000?????1010111")
def VMERGE_VVM = BitPat("b0101110??????????000?????1010111")
def VMV_V_V = BitPat("b010111100000?????000?????1010111")
def VMSEQ_VV = BitPat("b011000???????????000?????1010111")
Expand All @@ -492,9 +488,7 @@ object Instructions {
def VSADD_VV = BitPat("b100001???????????000?????1010111")
def VSSUBU_VV = BitPat("b100010???????????000?????1010111")
def VSSUB_VV = BitPat("b100011???????????000?????1010111")
def VAADD_VV = BitPat("b100100???????????000?????1010111")
def VSLL_VV = BitPat("b100101???????????000?????1010111")
def VASUB_VV = BitPat("b100110???????????000?????1010111")
def VSMUL_VV = BitPat("b100111???????????000?????1010111")
def VSRL_VV = BitPat("b101000???????????000?????1010111")
def VSRA_VV = BitPat("b101001???????????000?????1010111")
Expand All @@ -508,9 +502,6 @@ object Instructions {
def VWREDSUM_VS = BitPat("b110001???????????000?????1010111")
def VDOTU_VV = BitPat("b111000???????????000?????1010111")
def VDOT_VV = BitPat("b111001???????????000?????1010111")
def VWSMACCU_VV = BitPat("b111100???????????000?????1010111")
def VWSMACC_VV = BitPat("b111101???????????000?????1010111")
def VWSMACCSU_VV = BitPat("b111111???????????000?????1010111")
def VADD_VI = BitPat("b000000???????????011?????1010111")
def VRSUB_VI = BitPat("b000011???????????011?????1010111")
def VAND_VI = BitPat("b001001???????????011?????1010111")
Expand All @@ -519,8 +510,8 @@ object Instructions {
def VRGATHER_VI = BitPat("b001100???????????011?????1010111")
def VSLIDEUP_VI = BitPat("b001110???????????011?????1010111")
def VSLIDEDOWN_VI = BitPat("b001111???????????011?????1010111")
def VADC_VIM = BitPat("b0100001??????????011?????1010111")
def VMADC_VIM = BitPat("b0100011??????????011?????1010111")
def VADC_VIM = BitPat("b0100000??????????011?????1010111")
def VMADC_VIM = BitPat("b010001???????????011?????1010111")
def VMERGE_VIM = BitPat("b0101110??????????011?????1010111")
def VMV_V_I = BitPat("b010111100000?????011?????1010111")
def VMSEQ_VI = BitPat("b011000???????????011?????1010111")
Expand All @@ -531,8 +522,8 @@ object Instructions {
def VMSGT_VI = BitPat("b011111???????????011?????1010111")
def VSADDU_VI = BitPat("b100000???????????011?????1010111")
def VSADD_VI = BitPat("b100001???????????011?????1010111")
def VAADD_VI = BitPat("b100100???????????011?????1010111")
def VSLL_VI = BitPat("b100101???????????011?????1010111")
def VMVR_V = BitPat("b1001111??????????011?????1010111")
def VSRL_VI = BitPat("b101000???????????011?????1010111")
def VSRA_VI = BitPat("b101001???????????011?????1010111")
def VSSRL_VI = BitPat("b101010???????????011?????1010111")
Expand All @@ -549,8 +540,12 @@ object Instructions {
def VREDMIN_VS = BitPat("b000101???????????010?????1010111")
def VREDMAXU_VS = BitPat("b000110???????????010?????1010111")
def VREDMAX_VS = BitPat("b000111???????????010?????1010111")
def VAADDU_VV = BitPat("b001000???????????010?????1010111")
def VAADD_VV = BitPat("b001001???????????010?????1010111")
def VASUBU_VV = BitPat("b001010???????????010?????1010111")
def VASUB_VV = BitPat("b001011???????????010?????1010111")
def VMV_X_S = BitPat("b0100001?????00000010?????1010111")
def VCOMPRESS_VM = BitPat("b010111???????????010?????1010111")
def VCOMPRESS_VM = BitPat("b0101111??????????010?????1010111")
def VMANDNOT_MM = BitPat("b011000???????????010?????1010111")
def VMAND_MM = BitPat("b011001???????????010?????1010111")
def VMOR_MM = BitPat("b011010???????????010?????1010111")
Expand Down Expand Up @@ -592,6 +587,10 @@ object Instructions {
def VWMACCU_VV = BitPat("b111100???????????010?????1010111")
def VWMACC_VV = BitPat("b111101???????????010?????1010111")
def VWMACCSU_VV = BitPat("b111111???????????010?????1010111")
def VAADDU_VX = BitPat("b001000???????????110?????1010111")
def VAADD_VX = BitPat("b001001???????????110?????1010111")
def VASUBU_VX = BitPat("b001010???????????110?????1010111")
def VASUB_VX = BitPat("b001011???????????110?????1010111")
def VMV_S_X = BitPat("b010000100000?????110?????1010111")
def VSLIDE1UP_VX = BitPat("b001110???????????110?????1010111")
def VSLIDE1DOWN_VX = BitPat("b001111???????????110?????1010111")
Expand Down Expand Up @@ -671,6 +670,7 @@ object Instructions {
def FMV_X_S = BitPat("b111000000000?????000?????1010011")
def FMV_S_X = BitPat("b111100000000?????000?????1010011")
def FENCE_TSO = BitPat("b100000110011?????000?????0001111")
def PAUSE = BitPat("b00000001000000000000000000001111")
}
object Causes {
val misaligned_fetch = 0x0
Expand Down Expand Up @@ -757,6 +757,7 @@ object CSRs {
val hpmcounter31 = 0xc1f
val vl = 0xc20
val vtype = 0xc21
val vlenb = 0xc22
val sstatus = 0x100
val sie = 0x104
val stvec = 0x105
Expand Down Expand Up @@ -1012,6 +1013,7 @@ object CSRs {
res += hpmcounter31
res += vl
res += vtype
res += vlenb
res += sstatus
res += sie
res += stvec
Expand Down

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