Connect optional trace stall

src/main/scala/rocket/CSR.scala

@@ -172,6 +172,10 @@ class TracedInstruction(implicit p: Parameters) extends CoreBundle with Clocked
   val tval = UInt(width = coreMaxAddrBits max iLen)
 }
 
+class TraceAux extends Bundle {
+  val stall = Bool()
+}
+
 class CSRDecodeIO extends Bundle {
   val csr = UInt(INPUT, CSR.ADDRSZ)
   val fp_illegal = Bool(OUTPUT)

src/main/scala/rocket/RocketCore.scala

@@ -754,7 +754,8 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
     !clock_en ||
     id_do_fence ||
     csr.io.csr_stall ||
-    id_reg_pause
+    id_reg_pause ||
+    io.traceStall
   ctrl_killd := !ibuf.io.inst(0).valid || ibuf.io.inst(0).bits.replay || take_pc_mem_wb || ctrl_stalld || csr.io.interrupt
 
   io.imem.req.valid := take_pc

src/main/scala/tile/BaseTile.scala

@@ -174,6 +174,11 @@ abstract class BaseTile private (val crossing: ClockCrossingType, q: Parameters)
   val traceNode = BundleBroadcast[Vec[TracedInstruction]](Some("trace"))
   traceNode := traceSourceNode
 
+  val traceAuxNode = BundleBridgeNexus[TraceAux]()
+  val traceAuxSinkNode = BundleBridgeSink[TraceAux]()
+  val traceAuxDefaultNode = BundleBridgeSource(() => new TraceAux)
+  traceAuxSinkNode := traceAuxNode := traceAuxDefaultNode
+
   val bpwatchSourceNode = BundleBridgeSource(() => Vec(tileParams.core.nBreakpoints, new BPWatch(tileParams.core.retireWidth)))
   val bpwatchNode = BundleBroadcast[Vec[BPWatch]](Some("bpwatch"))
   bpwatchNode := bpwatchSourceNode
@@ -245,6 +250,10 @@ abstract class BaseTileModuleImp[+L <: BaseTile](val outer: L) extends LazyModul
   require(resetVectorLen <= vaddrBitsExtended)
   require (log2Up(hartId + 1) <= hartIdLen, s"p(MaxHartIdBits) of $hartIdLen is not enough for hartid $hartId")
 
+  outer.traceAuxDefaultNode.bundle.stall := false.B
+  val (in, _) = outer.traceAuxNode.in.last   // select active source if any, or the default source
+  outer.traceAuxNode.out.foreach { case (out, _) => out := in }
+
   val constants = IO(new TileInputConstants)
 }
 

src/main/scala/tile/Core.scala

@@ -125,5 +125,6 @@ trait HasCoreIO extends HasTileParameters {
     val trace = Vec(coreParams.retireWidth, new TracedInstruction).asOutput
     val bpwatch = Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth)).asOutput
     val cease = Bool().asOutput
+    val traceStall = Bool().asInput
   }
 }

src/main/scala/tile/RocketTile.scala

@@ -147,6 +147,7 @@ class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer)
 
   // Pass through various external constants and reports
   outer.traceSourceNode.bundle <> core.io.trace
+  core.io.traceStall := outer.traceAuxSinkNode.bundle.stall
   outer.bpwatchSourceNode.bundle <> core.io.bpwatch
   core.io.hartid := constants.hartid
   outer.dcache.module.io.hartid := constants.hartid