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This is a simple example LLVM backend for an UPT architecture - An self define CPU for my master degree thesis
todo
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I will update some practical videos and documentation for the development of the compiler backend
Except for those related to code generation algorithms such as instruction selection and register allocation,there are few papers involved here, as most of them are not practical
A good place is [llvm dev mailing list],you can find answers for those tricky problem in practical banckend development
Hopefully it will help you
2019 LLVM Developers’ Meeting: J. Paquette & F. Hahn “Getting Started With LLVM: Basics”
2019 LLVM Developers’ Meeting: E. Christopher & J. Doerfert “Introduction to LLVM”
http://llvm.org/docs/TableGen/index.html
http://llvm.org/docs/TableGen/LangIntro.html
http://llvm.org/devmtg/2019-04/slides/Tutorial-Bridgers-LLVM_IR_tutorial.pdf
The LLVM Machine Representation
http://blog.llvm.org/2010/04/intro-to-llvm-mc-project.html
https://www.embecosm.com/appnotes/ean10/ean10-howto-llvmas-1.0.html
http://llvm.org/docs/CodeGenerator.html
https://llvm.org/docs/WritingAnLLVMBackend.html
Tutorial: Creating an LLVM Backend for the Cpu0 Architecture
https://github.com/FrozenGene/presentation/blob/master/pdf/LLVM.pdf
https://www.cs.cmu.edu/afs/cs/academic/class/15745-s11/public/lectures/
https://lagunita.stanford.edu/login?next=/courses/Engineering/Compilers/Fall2014/course
Instruction selection: principles, methods, and applications
2016 LLVM Developers’ Meeting: A. Bougacha & Q. Colombet & T. Northover “Global Instr.."
GlobalISel - LLVM's Latest Instruction Selection Framework
2017 LLVM Developers’ Meeting: “GlobalISel: Past, Present, and Future ”
https://en.wikipedia.org/wiki/Instruction_scheduling
https://engineering.purdue.edu/~milind/ece468/2015fall/lecture-08-6up.pdf
https://www.cl.cam.ac.uk/teaching/2005/OptComp/slides/lecture14.pdf
http://infolab.stanford.edu/~ullman/dragon/w06/lectures/inst-sched.pdf
2017 LLVM Developers’ Meeting: “Writing Great Machine Schedulers ”
http://llvm.org/devmtg/2012-11/Larin-Trick-Scheduling.pdf
https://llvm.org/devmtg/2014-10/Slides/Estes-MISchedulerTutorial.pdf
LLVM Instruction Scheduling (MI Scheduler)
Latency Calculation in Instruction Scheduling
http://blog.llvm.org/2011/09/greedy-register-allocation-in-llvm-30.html
Slot Index, Live Range, and Live Interval
2018 LLVM Developers’ Meeting: M. Braun “Register Allocation: More than Coloring”
Linear Scan register allocation for the Java HotSpot client compiler
https://en.wikipedia.org/wiki/Linker_(computing)#Relocation
Relaxation in Debug Information
http://llvm.org/docs/TestingGuide.html
2019 LLVM Developers’ Meeting: Homerding & Kruse “Getting Started with the LLVM Testing Infra..”
https://llvm.org/docs/CommandGuide/FileCheck.html
2018 LLVM Developers’ Meeting: A. Bradbury “LLVM backend development by example (RISC-V)”
2019 LLVM Developers’ Meeting: A. Bradbury “Maturing an LLVM backend: Lessons learned from the...”
https://reup.dmcs.pl/wiki/images/7/7a/Tricore-llvm-slides.pdf
llvm riscv backend commit patches
Leon llvm backend Goldberg C J. The Design of a Custom 32-bit RISC CPU and LLVM Compiler Backend[J], 2017.
https://courses.cs.washington.edu/courses/cse410/09sp/examples/MIPSCallingConventionsSummary.pdf
Parameter (computer programming)
http://user.it.uu.se/~kostis/Teaching/KT1-11/Slides/handout13.pdf
LLVM:PowerPC assembly language tour
http://jonathan2251.github.io/lbd/funccall.html#dynamic-stack-allocation-support