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[mips][wasm-simd] Implement double precision conversion
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Port: 3b6eb33

Bug: v8:11265

Change-Id: I6ecd95e64b18a8f45f0aaa2f40d15f8c8cd43340
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2704212
Auto-Submit: Liu yu <[email protected]>
Reviewed-by: Zhao Jiazhong <[email protected]>
Commit-Queue: Zhao Jiazhong <[email protected]>
Cr-Commit-Position: refs/heads/master@{#72842}
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@LiuYu396
LiuYu396 authored and Commit Bot committed Feb 18, 2021
1 parent f3ec6d7 commit a375246
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Showing 8 changed files with 219 additions and 91 deletions.
46 changes: 46 additions & 0 deletions src/compiler/backend/mips/code-generator-mips.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -2202,6 +2202,27 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ ctcmsa(MSACSR, kScratchReg);
break;
}
case kMipsF64x2ConvertLowI32x4S: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ ilvr_w(kSimd128RegZero, kSimd128RegZero, i.InputSimd128Register(0));
__ slli_d(kSimd128RegZero, kSimd128RegZero, 32);
__ srai_d(kSimd128RegZero, kSimd128RegZero, 32);
__ ffint_s_d(i.OutputSimd128Register(), kSimd128RegZero);
break;
}
case kMipsF64x2ConvertLowI32x4U: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ ilvr_w(kSimd128RegZero, kSimd128RegZero, i.InputSimd128Register(0));
__ ffint_u_d(i.OutputSimd128Register(), kSimd128RegZero);
break;
}
case kMipsF64x2PromoteLowF32x4: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fexupr_d(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kMipsI64x2Add: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ addv_d(i.OutputSimd128Register(), i.InputSimd128Register(0),
Expand Down Expand Up @@ -2365,6 +2386,13 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ ffint_u_w(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kMipsF32x4DemoteF64x2Zero: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ fexdo_w(i.OutputSimd128Register(), kSimd128RegZero,
i.InputSimd128Register(0));
break;
}
case kMipsI32x4Mul: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ mulv_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
Expand Down Expand Up @@ -2649,6 +2677,24 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(1));
break;
}
case kMipsI32x4TruncSatF64x2SZero: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ ftrunc_s_d(kSimd128ScratchReg, i.InputSimd128Register(0));
__ sat_s_d(kSimd128ScratchReg, kSimd128ScratchReg, 31);
__ pckev_w(i.OutputSimd128Register(), kSimd128RegZero,
kSimd128ScratchReg);
break;
}
case kMipsI32x4TruncSatF64x2UZero: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ ftrunc_u_d(kSimd128ScratchReg, i.InputSimd128Register(0));
__ sat_u_d(kSimd128ScratchReg, kSimd128ScratchReg, 31);
__ pckev_w(i.OutputSimd128Register(), kSimd128RegZero,
kSimd128ScratchReg);
break;
}
case kMipsI16x8Splat: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fill_h(i.OutputSimd128Register(), i.InputRegister(0));
Expand Down
6 changes: 6 additions & 0 deletions src/compiler/backend/mips/instruction-codes-mips.h
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Original file line number Diff line number Diff line change
Expand Up @@ -160,6 +160,9 @@ namespace compiler {
V(MipsF64x2Floor) \
V(MipsF64x2Trunc) \
V(MipsF64x2NearestInt) \
V(MipsF64x2ConvertLowI32x4S) \
V(MipsF64x2ConvertLowI32x4U) \
V(MipsF64x2PromoteLowF32x4) \
V(MipsI64x2Add) \
V(MipsI64x2Sub) \
V(MipsI64x2Mul) \
Expand All @@ -182,6 +185,7 @@ namespace compiler {
V(MipsF32x4ReplaceLane) \
V(MipsF32x4SConvertI32x4) \
V(MipsF32x4UConvertI32x4) \
V(MipsF32x4DemoteF64x2Zero) \
V(MipsI32x4Mul) \
V(MipsI32x4MaxS) \
V(MipsI32x4MinS) \
Expand Down Expand Up @@ -231,6 +235,8 @@ namespace compiler {
V(MipsI32x4ExtMulHighI16x8S) \
V(MipsI32x4ExtMulLowI16x8U) \
V(MipsI32x4ExtMulHighI16x8U) \
V(MipsI32x4TruncSatF64x2SZero) \
V(MipsI32x4TruncSatF64x2UZero) \
V(MipsI16x8Splat) \
V(MipsI16x8ExtractLaneU) \
V(MipsI16x8ExtractLaneS) \
Expand Down
6 changes: 6 additions & 0 deletions src/compiler/backend/mips/instruction-scheduler-mips.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -63,6 +63,9 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMipsF64x2Floor:
case kMipsF64x2Trunc:
case kMipsF64x2NearestInt:
case kMipsF64x2ConvertLowI32x4S:
case kMipsF64x2ConvertLowI32x4U:
case kMipsF64x2PromoteLowF32x4:
case kMipsI64x2Add:
case kMipsI64x2Sub:
case kMipsI64x2Mul:
Expand Down Expand Up @@ -107,6 +110,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMipsF32x4Floor:
case kMipsF32x4Trunc:
case kMipsF32x4NearestInt:
case kMipsF32x4DemoteF64x2Zero:
case kMipsFloat32Max:
case kMipsFloat32Min:
case kMipsFloat32RoundDown:
Expand Down Expand Up @@ -200,6 +204,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMipsI32x4ExtMulHighI16x8S:
case kMipsI32x4ExtMulLowI16x8U:
case kMipsI32x4ExtMulHighI16x8U:
case kMipsI32x4TruncSatF64x2SZero:
case kMipsI32x4TruncSatF64x2UZero:
case kMipsI8x16Add:
case kMipsI8x16AddSatS:
case kMipsI8x16AddSatU:
Expand Down
90 changes: 48 additions & 42 deletions src/compiler/backend/mips/instruction-selector-mips.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -2115,48 +2115,54 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I16x8) \
V(I8x16)

#define SIMD_UNOP_LIST(V) \
V(F64x2Abs, kMipsF64x2Abs) \
V(F64x2Neg, kMipsF64x2Neg) \
V(F64x2Sqrt, kMipsF64x2Sqrt) \
V(F64x2Ceil, kMipsF64x2Ceil) \
V(F64x2Floor, kMipsF64x2Floor) \
V(F64x2Trunc, kMipsF64x2Trunc) \
V(F64x2NearestInt, kMipsF64x2NearestInt) \
V(I64x2Neg, kMipsI64x2Neg) \
V(I64x2BitMask, kMipsI64x2BitMask) \
V(F32x4SConvertI32x4, kMipsF32x4SConvertI32x4) \
V(F32x4UConvertI32x4, kMipsF32x4UConvertI32x4) \
V(F32x4Abs, kMipsF32x4Abs) \
V(F32x4Neg, kMipsF32x4Neg) \
V(F32x4Sqrt, kMipsF32x4Sqrt) \
V(F32x4RecipApprox, kMipsF32x4RecipApprox) \
V(F32x4RecipSqrtApprox, kMipsF32x4RecipSqrtApprox) \
V(F32x4Ceil, kMipsF32x4Ceil) \
V(F32x4Floor, kMipsF32x4Floor) \
V(F32x4Trunc, kMipsF32x4Trunc) \
V(F32x4NearestInt, kMipsF32x4NearestInt) \
V(I32x4SConvertF32x4, kMipsI32x4SConvertF32x4) \
V(I32x4UConvertF32x4, kMipsI32x4UConvertF32x4) \
V(I32x4Neg, kMipsI32x4Neg) \
V(I32x4BitMask, kMipsI32x4BitMask) \
V(I32x4SConvertI16x8Low, kMipsI32x4SConvertI16x8Low) \
V(I32x4SConvertI16x8High, kMipsI32x4SConvertI16x8High) \
V(I32x4UConvertI16x8Low, kMipsI32x4UConvertI16x8Low) \
V(I32x4UConvertI16x8High, kMipsI32x4UConvertI16x8High) \
V(I16x8Neg, kMipsI16x8Neg) \
V(I16x8BitMask, kMipsI16x8BitMask) \
V(I16x8SConvertI8x16Low, kMipsI16x8SConvertI8x16Low) \
V(I16x8SConvertI8x16High, kMipsI16x8SConvertI8x16High) \
V(I16x8UConvertI8x16Low, kMipsI16x8UConvertI8x16Low) \
V(I16x8UConvertI8x16High, kMipsI16x8UConvertI8x16High) \
V(I8x16Neg, kMipsI8x16Neg) \
V(I8x16Popcnt, kMipsI8x16Popcnt) \
V(I8x16BitMask, kMipsI8x16BitMask) \
V(S128Not, kMipsS128Not) \
V(V32x4AllTrue, kMipsV32x4AllTrue) \
V(V16x8AllTrue, kMipsV16x8AllTrue) \
V(V8x16AllTrue, kMipsV8x16AllTrue) \
#define SIMD_UNOP_LIST(V) \
V(F64x2Abs, kMipsF64x2Abs) \
V(F64x2Neg, kMipsF64x2Neg) \
V(F64x2Sqrt, kMipsF64x2Sqrt) \
V(F64x2Ceil, kMipsF64x2Ceil) \
V(F64x2Floor, kMipsF64x2Floor) \
V(F64x2Trunc, kMipsF64x2Trunc) \
V(F64x2NearestInt, kMipsF64x2NearestInt) \
V(F64x2ConvertLowI32x4S, kMipsF64x2ConvertLowI32x4S) \
V(F64x2ConvertLowI32x4U, kMipsF64x2ConvertLowI32x4U) \
V(F64x2PromoteLowF32x4, kMipsF64x2PromoteLowF32x4) \
V(I64x2Neg, kMipsI64x2Neg) \
V(I64x2BitMask, kMipsI64x2BitMask) \
V(F32x4SConvertI32x4, kMipsF32x4SConvertI32x4) \
V(F32x4UConvertI32x4, kMipsF32x4UConvertI32x4) \
V(F32x4Abs, kMipsF32x4Abs) \
V(F32x4Neg, kMipsF32x4Neg) \
V(F32x4Sqrt, kMipsF32x4Sqrt) \
V(F32x4RecipApprox, kMipsF32x4RecipApprox) \
V(F32x4RecipSqrtApprox, kMipsF32x4RecipSqrtApprox) \
V(F32x4Ceil, kMipsF32x4Ceil) \
V(F32x4Floor, kMipsF32x4Floor) \
V(F32x4Trunc, kMipsF32x4Trunc) \
V(F32x4NearestInt, kMipsF32x4NearestInt) \
V(F32x4DemoteF64x2Zero, kMipsF32x4DemoteF64x2Zero) \
V(I32x4SConvertF32x4, kMipsI32x4SConvertF32x4) \
V(I32x4UConvertF32x4, kMipsI32x4UConvertF32x4) \
V(I32x4Neg, kMipsI32x4Neg) \
V(I32x4BitMask, kMipsI32x4BitMask) \
V(I32x4SConvertI16x8Low, kMipsI32x4SConvertI16x8Low) \
V(I32x4SConvertI16x8High, kMipsI32x4SConvertI16x8High) \
V(I32x4UConvertI16x8Low, kMipsI32x4UConvertI16x8Low) \
V(I32x4UConvertI16x8High, kMipsI32x4UConvertI16x8High) \
V(I32x4TruncSatF64x2SZero, kMipsI32x4TruncSatF64x2SZero) \
V(I32x4TruncSatF64x2UZero, kMipsI32x4TruncSatF64x2UZero) \
V(I16x8Neg, kMipsI16x8Neg) \
V(I16x8BitMask, kMipsI16x8BitMask) \
V(I16x8SConvertI8x16Low, kMipsI16x8SConvertI8x16Low) \
V(I16x8SConvertI8x16High, kMipsI16x8SConvertI8x16High) \
V(I16x8UConvertI8x16Low, kMipsI16x8UConvertI8x16Low) \
V(I16x8UConvertI8x16High, kMipsI16x8UConvertI8x16High) \
V(I8x16Neg, kMipsI8x16Neg) \
V(I8x16Popcnt, kMipsI8x16Popcnt) \
V(I8x16BitMask, kMipsI8x16BitMask) \
V(S128Not, kMipsS128Not) \
V(V32x4AllTrue, kMipsV32x4AllTrue) \
V(V16x8AllTrue, kMipsV16x8AllTrue) \
V(V8x16AllTrue, kMipsV8x16AllTrue) \
V(V128AnyTrue, kMipsV128AnyTrue)

#define SIMD_SHIFT_OP_LIST(V) \
Expand Down
46 changes: 46 additions & 0 deletions src/compiler/backend/mips64/code-generator-mips64.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -2316,6 +2316,27 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
kRoundToNearest);
break;
}
case kMips64F64x2ConvertLowI32x4S: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ ilvr_w(kSimd128RegZero, kSimd128RegZero, i.InputSimd128Register(0));
__ slli_d(kSimd128RegZero, kSimd128RegZero, 32);
__ srai_d(kSimd128RegZero, kSimd128RegZero, 32);
__ ffint_s_d(i.OutputSimd128Register(), kSimd128RegZero);
break;
}
case kMips64F64x2ConvertLowI32x4U: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ ilvr_w(kSimd128RegZero, kSimd128RegZero, i.InputSimd128Register(0));
__ ffint_u_d(i.OutputSimd128Register(), kSimd128RegZero);
break;
}
case kMips64F64x2PromoteLowF32x4: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fexupr_d(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kMips64I64x2ReplaceLane: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
Simd128Register src = i.InputSimd128Register(0);
Expand Down Expand Up @@ -2737,6 +2758,13 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
kRoundToNearest);
break;
}
case kMips64F32x4DemoteF64x2Zero: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ fexdo_w(i.OutputSimd128Register(), kSimd128RegZero,
i.InputSimd128Register(0));
break;
}
case kMips64I32x4SConvertF32x4: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ ftrunc_s_w(i.OutputSimd128Register(), i.InputSimd128Register(0));
Expand Down Expand Up @@ -2811,6 +2839,24 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
i.InputSimd128Register(1));
break;
}
case kMips64I32x4TruncSatF64x2SZero: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ ftrunc_s_d(kSimd128ScratchReg, i.InputSimd128Register(0));
__ sat_s_d(kSimd128ScratchReg, kSimd128ScratchReg, 31);
__ pckev_w(i.OutputSimd128Register(), kSimd128RegZero,
kSimd128ScratchReg);
break;
}
case kMips64I32x4TruncSatF64x2UZero: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ ftrunc_u_d(kSimd128ScratchReg, i.InputSimd128Register(0));
__ sat_u_d(kSimd128ScratchReg, kSimd128ScratchReg, 31);
__ pckev_w(i.OutputSimd128Register(), kSimd128RegZero,
kSimd128ScratchReg);
break;
}
case kMips64I16x8Splat: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fill_h(i.OutputSimd128Register(), i.InputRegister(0));
Expand Down
6 changes: 6 additions & 0 deletions src/compiler/backend/mips64/instruction-codes-mips64.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -210,6 +210,9 @@ namespace compiler {
V(Mips64F64x2Floor) \
V(Mips64F64x2Trunc) \
V(Mips64F64x2NearestInt) \
V(Mips64F64x2ConvertLowI32x4S) \
V(Mips64F64x2ConvertLowI32x4U) \
V(Mips64F64x2PromoteLowF32x4) \
V(Mips64I64x2Splat) \
V(Mips64I64x2ExtractLane) \
V(Mips64I64x2ReplaceLane) \
Expand Down Expand Up @@ -250,6 +253,7 @@ namespace compiler {
V(Mips64F32x4Floor) \
V(Mips64F32x4Trunc) \
V(Mips64F32x4NearestInt) \
V(Mips64F32x4DemoteF64x2Zero) \
V(Mips64I32x4SConvertF32x4) \
V(Mips64I32x4UConvertF32x4) \
V(Mips64I32x4Neg) \
Expand All @@ -260,6 +264,8 @@ namespace compiler {
V(Mips64I32x4Abs) \
V(Mips64I32x4BitMask) \
V(Mips64I32x4DotI16x8S) \
V(Mips64I32x4TruncSatF64x2SZero) \
V(Mips64I32x4TruncSatF64x2UZero) \
V(Mips64I16x8Splat) \
V(Mips64I16x8ExtractLaneU) \
V(Mips64I16x8ExtractLaneS) \
Expand Down
6 changes: 6 additions & 0 deletions src/compiler/backend/mips64/instruction-scheduler-mips64.cc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -88,6 +88,9 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMips64F64x2Floor:
case kMips64F64x2Trunc:
case kMips64F64x2NearestInt:
case kMips64F64x2ConvertLowI32x4S:
case kMips64F64x2ConvertLowI32x4U:
case kMips64F64x2PromoteLowF32x4:
case kMips64I64x2Splat:
case kMips64I64x2ExtractLane:
case kMips64I64x2ReplaceLane:
Expand Down Expand Up @@ -133,6 +136,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMips64F32x4Floor:
case kMips64F32x4Trunc:
case kMips64F32x4NearestInt:
case kMips64F32x4DemoteF64x2Zero:
case kMips64F64x2Splat:
case kMips64F64x2ExtractLane:
case kMips64F64x2ReplaceLane:
Expand Down Expand Up @@ -223,6 +227,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kMips64I32x4Abs:
case kMips64I32x4BitMask:
case kMips64I32x4DotI16x8S:
case kMips64I32x4TruncSatF64x2SZero:
case kMips64I32x4TruncSatF64x2UZero:
case kMips64I8x16Add:
case kMips64I8x16AddSatS:
case kMips64I8x16AddSatU:
Expand Down
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