This is a FPGA supported RISC-V CPU with 5-stage pipeline and 2-way set associative cache implemented in Verilog HDL. This is a course project for Computer Architecture 2018(MS108), ACM honor class 2017, SJTU. Written in 2018.
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This is a FPGA supported RISC-V CPU with 5-stage pipeline and 2-way set associative cache implemented in Verilog HDL.
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