target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte…

… memory access insted of 4 Signed-off-by: Bastian Koppelmann <[email protected]>
zhijianli88 · May 11, 2015 · 7bd0eae · 7bd0eae
1 parent 250ef8c
commit 7bd0eae
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
@@ -3745,10 +3745,10 @@ static void decode_slr_opc(DisasContext *ctx, int op1)
         tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
         break;
     case OPC1_16_SLR_LD_W:
-        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
+        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
         break;
     case OPC1_16_SLR_LD_W_POSTINC:
-        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
+        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
         tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
         break;
     }