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tests/tcg/s390x: Fix EXRL tests
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The current EXRL tests crash on real machines: we must not use r0 as a base
register for trt/trtr, otherwise the content gets ignored. Also, we must
not use r0 for exrl, otherwise it gets ignored.

Let's use the "a" constraint so we get a general purpose register != r0.
For op2, we can simply specify a memory operand directly via "Q" (Memory
reference without index register and with short displacement).

Fixes: ad8c851 ("target/s390x: add EX support for TRT and TRTR")
Signed-off-by: David Hildenbrand <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Cornelia Huck <[email protected]>
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davidhildenbrand authored and cohuck committed Jan 21, 2021
1 parent 401bf46 commit d944293
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Showing 2 changed files with 8 additions and 8 deletions.
8 changes: 4 additions & 4 deletions tests/tcg/s390x/exrl-trt.c
Original file line number Diff line number Diff line change
Expand Up @@ -19,17 +19,17 @@ int main(void)
}
asm volatile(
" j 2f\n"
"1: trt 0(1,%[op1]),0(%[op2])\n"
"1: trt 0(1,%[op1]),%[op2]\n"
"2: exrl %[op1_len],1b\n"
" lgr %[r1],%%r1\n"
" lgr %[r2],%%r2\n"
" ipm %[cc]\n"
: [r1] "+r" (r1),
[r2] "+r" (r2),
[cc] "=r" (cc)
: [op1] "r" (&op1),
[op1_len] "r" (5),
[op2] "r" (&op2)
: [op1] "a" (&op1),
[op1_len] "a" (5),
[op2] "Q" (op2)
: "r1", "r2", "cc");
cc = (cc >> 28) & 3;
if (cc != 2) {
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8 changes: 4 additions & 4 deletions tests/tcg/s390x/exrl-trtr.c
Original file line number Diff line number Diff line change
Expand Up @@ -19,17 +19,17 @@ int main(void)
}
asm volatile(
" j 2f\n"
"1: trtr 3(1,%[op1]),0(%[op2])\n"
"1: trtr 3(1,%[op1]),%[op2]\n"
"2: exrl %[op1_len],1b\n"
" lgr %[r1],%%r1\n"
" lgr %[r2],%%r2\n"
" ipm %[cc]\n"
: [r1] "+r" (r1),
[r2] "+r" (r2),
[cc] "=r" (cc)
: [op1] "r" (&op1),
[op1_len] "r" (3),
[op2] "r" (&op2)
: [op1] "a" (&op1),
[op1_len] "a" (3),
[op2] "Q" (op2)
: "r1", "r2", "cc");
cc = (cc >> 28) & 3;
if (cc != 1) {
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