MIPS: CM: Fix GCR_Cx_CONFIG PVPE mask

The PVPE (or PVP in >= CM3) field is 10 bits wide, but the mask previously only covered the bottom 9 bits. Extend the mask to cover all 10 bits of the field. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: [email protected] Cc: James Hogan <[email protected]> Cc: Markos Chandras <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/11206/ Signed-off-by: Ralf Baechle <[email protected]>
zhudingsuifeng · Nov 11, 2015 · 252d6aa · 252d6aa
1 parent a8c2061
commit 252d6aa
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
@@ -359,7 +359,7 @@ BUILD_CM_Cx_R_(tcid_8_priority,	0x80)
 #define CM_GCR_Cx_CONFIG_IOCUTYPE_SHF		10
 #define CM_GCR_Cx_CONFIG_IOCUTYPE_MSK		(_ULCAST_(0x3) << 10)
 #define CM_GCR_Cx_CONFIG_PVPE_SHF		0
-#define CM_GCR_Cx_CONFIG_PVPE_MSK		(_ULCAST_(0x1ff) << 0)
+#define CM_GCR_Cx_CONFIG_PVPE_MSK		(_ULCAST_(0x3ff) << 0)
 
 /* GCR_Cx_OTHER register fields */
 #define CM_GCR_Cx_OTHER_CORENUM_SHF		16