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[ARM] Replace HasT2ExtractPack with HasDSP
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Removed the HasT2ExtractPack feature and replaced its references
with HasDSP. This then allows the Thumb2 extend instructions to be
selected for ARMv8M +dsp. These instruction descriptions have also
been refactored and more target tests have been added for their isel.

Differential Revision: https://reviews.llvm.org/D29623


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295452 91177308-0d34-0410-b5e6-96231b3b80d8
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@sparker-arm
sparker-arm committed Feb 17, 2017
1 parent 2566cbc commit 50a37dc
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Showing 10 changed files with 217 additions and 260 deletions.
22 changes: 6 additions & 16 deletions lib/Target/ARM/ARM.td
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Original file line number Diff line number Diff line change
Expand Up @@ -72,8 +72,6 @@ def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
"HasHardwareDivideInARM", "true",
"Enable divide instructions in ARM mode">;
def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
"Enable Thumb2 extract and pack instructions">;
def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
"Has data barrier (dmb / dsb) instructions">;
def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
Expand Down Expand Up @@ -297,8 +295,7 @@ def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
FeatureV7Clrex]>;
def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
"Support ARM v8 instructions",
[HasV7Ops, FeatureAcquireRelease,
FeatureT2XtPk]>;
[HasV7Ops, FeatureAcquireRelease]>;
def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
"Support ARM v8.1a instructions",
[HasV8Ops]>;
Expand Down Expand Up @@ -393,8 +390,7 @@ def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>;
def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops]>;

def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops,
FeatureDSP,
FeatureT2XtPk]>;
FeatureDSP]>;

def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>;

Expand All @@ -415,8 +411,7 @@ def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops,
FeatureNEON,
FeatureDB,
FeatureDSP,
FeatureAClass,
FeatureT2XtPk]>;
FeatureAClass]>;

def ARMv7ve : Architecture<"armv7ve", "ARMv7ve", [HasV7Ops,
FeatureNEON,
Expand All @@ -425,15 +420,13 @@ def ARMv7ve : Architecture<"armv7ve", "ARMv7ve", [HasV7Ops,
FeatureTrustZone,
FeatureMP,
FeatureVirtualization,
FeatureAClass,
FeatureT2XtPk]>;
FeatureAClass]>;

def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops,
FeatureDB,
FeatureDSP,
FeatureHWDiv,
FeatureRClass,
FeatureT2XtPk]>;
FeatureRClass]>;

def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops,
FeatureThumb2,
Expand All @@ -448,8 +441,7 @@ def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops,
FeatureDB,
FeatureHWDiv,
FeatureMClass,
FeatureDSP,
FeatureT2XtPk]>;
FeatureDSP]>;

def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops,
FeatureAClass,
Expand Down Expand Up @@ -491,7 +483,6 @@ def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps,
def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops,
FeatureRClass,
FeatureDB,
FeatureT2XtPk,
FeatureDSP,
FeatureCRC,
FeatureMP,
Expand Down Expand Up @@ -764,7 +755,6 @@ def : ProcNoItin<"cortex-m23", [ARMv8mBaseline,

def : ProcNoItin<"cortex-m33", [ARMv8mMainline,
FeatureDSP,
FeatureT2XtPk,
FeatureFPARMv8,
FeatureD16,
FeatureVFPOnlySP]>;
Expand Down
4 changes: 2 additions & 2 deletions lib/Target/ARM/ARMISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -10031,7 +10031,7 @@ static SDValue PerformORCombine(SDNode *N,
(Mask == ~Mask2)) {
// The pack halfword instruction works better for masks that fit it,
// so use that when it's available.
if (Subtarget->hasT2ExtractPack() &&
if (Subtarget->hasDSP() &&
(Mask == 0xffff || Mask == 0xffff0000))
return SDValue();
// 2a
Expand All @@ -10047,7 +10047,7 @@ static SDValue PerformORCombine(SDNode *N,
(~Mask == Mask2)) {
// The pack halfword instruction works better for masks that fit it,
// so use that when it's available.
if (Subtarget->hasT2ExtractPack() &&
if (Subtarget->hasDSP() &&
(Mask2 == 0xffff || Mask2 == 0xffff0000))
return SDValue();
// 2b
Expand Down
3 changes: 0 additions & 3 deletions lib/Target/ARM/ARMInstrFormats.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1013,9 +1013,6 @@ class Thumb2DSPPat<dag pattern, dag result> : Pat<pattern, result> {
class Thumb2DSPMulPat<dag pattern, dag result> : Pat<pattern, result> {
list<Predicate> Predicates = [IsThumb2, UseMulOps, HasDSP];
}
class Thumb2ExtractPat<dag pattern, dag result> : Pat<pattern, result> {
list<Predicate> Predicates = [IsThumb2, HasT2ExtractPack];
}
//===----------------------------------------------------------------------===//
// Thumb Instruction Format Definitions.
//
Expand Down
3 changes: 0 additions & 3 deletions lib/Target/ARM/ARMInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -249,9 +249,6 @@ def HasDivide : Predicate<"Subtarget->hasDivide()">,
AssemblerPredicate<"FeatureHWDiv", "divide in THUMB">;
def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">;
def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
AssemblerPredicate<"FeatureT2XtPk",
"pack/extract">;
def HasDSP : Predicate<"Subtarget->hasDSP()">,
AssemblerPredicate<"FeatureDSP", "dsp">;
def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
Expand Down
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