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Revert r237046. See the testcase on the thread where r237046 was comm…
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…itted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237317 91177308-0d34-0410-b5e6-96231b3b80d8
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@nlewycky
nlewycky committed May 13, 2015
1 parent b96942f commit 172e8df
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Showing 6 changed files with 59 additions and 67 deletions.
9 changes: 5 additions & 4 deletions include/llvm/CodeGen/SelectionDAG.h
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Original file line number Diff line number Diff line change
Expand Up @@ -665,7 +665,7 @@ class SelectionDAG {
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT);
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N);
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
const SDNodeFlags *Flags = nullptr);
bool nuw = false, bool nsw = false, bool exact = false);
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
SDValue N3);
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
Expand Down Expand Up @@ -982,7 +982,8 @@ class SelectionDAG {

/// Get the specified node if it's already available, or else return NULL.
SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTs, ArrayRef<SDValue> Ops,
const SDNodeFlags *Flags = nullptr);
bool nuw = false, bool nsw = false,
bool exact = false);

/// Creates a SDDbgValue node.
SDDbgValue *getDbgValue(MDNode *Var, MDNode *Expr, SDNode *N, unsigned R,
Expand Down Expand Up @@ -1240,8 +1241,8 @@ class SelectionDAG {
void allnodes_clear();

BinarySDNode *GetBinarySDNode(unsigned Opcode, SDLoc DL, SDVTList VTs,
SDValue N1, SDValue N2,
const SDNodeFlags *Flags = nullptr);
SDValue N1, SDValue N2, bool nuw, bool nsw,
bool exact);

/// Look up the node specified by ID in CSEMap. If it exists, return it. If
/// not, return the insertion token that will make insertion faster. This
Expand Down
9 changes: 2 additions & 7 deletions include/llvm/CodeGen/SelectionDAGNodes.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1017,11 +1017,6 @@ static bool isBinOpWithFlags(unsigned Opcode) {
case ISD::ADD:
case ISD::SUB:
case ISD::SHL:
case ISD::FADD:
case ISD::FDIV:
case ISD::FMUL:
case ISD::FREM:
case ISD::FSUB:
return true;
default:
return false;
Expand All @@ -1034,8 +1029,8 @@ class BinaryWithFlagsSDNode : public BinarySDNode {
public:
SDNodeFlags Flags;
BinaryWithFlagsSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs,
SDValue X, SDValue Y, const SDNodeFlags &NodeFlags)
: BinarySDNode(Opc, Order, dl, VTs, X, Y), Flags(NodeFlags) {}
SDValue X, SDValue Y)
: BinarySDNode(Opc, Order, dl, VTs, X, Y), Flags() {}
static bool classof(const SDNode *N) {
return isBinOpWithFlags(N->getOpcode());
}
Expand Down
7 changes: 5 additions & 2 deletions lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1452,9 +1452,12 @@ SDValue DAGCombiner::combine(SDNode *N) {
if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
SDValue Ops[] = {N1, N0};
SDNode *CSENode;
if (const auto *BinNode = dyn_cast<BinaryWithFlagsSDNode>(N)) {
if (const BinaryWithFlagsSDNode *BinNode =
dyn_cast<BinaryWithFlagsSDNode>(N)) {
CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops,
&BinNode->Flags);
BinNode->Flags.hasNoUnsignedWrap(),
BinNode->Flags.hasNoSignedWrap(),
BinNode->Flags.hasExact());
} else {
CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops);
}
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72 changes: 41 additions & 31 deletions lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -399,22 +399,19 @@ static void AddNodeIDOperands(FoldingSetNodeID &ID,
ID.AddInteger(Op.getResNo());
}
}
/// Add logical or fast math flag values to FoldingSetNodeID value.
static void AddNodeIDFlags(FoldingSetNodeID &ID, unsigned Opcode,
const SDNodeFlags *Flags) {
if (!Flags || !isBinOpWithFlags(Opcode))
return;

unsigned RawFlags = Flags->getRawFlags();
// If no flags are set, do not alter the ID. This saves time and allows
// a gradual increase in API usage of the optional optimization flags.
if (RawFlags != 0)
ID.AddInteger(RawFlags);

static void AddBinaryNodeIDCustom(FoldingSetNodeID &ID, bool nuw, bool nsw,
bool exact) {
ID.AddBoolean(nuw);
ID.AddBoolean(nsw);
ID.AddBoolean(exact);
}

static void AddNodeIDFlags(FoldingSetNodeID &ID, const SDNode *N) {
if (auto *Node = dyn_cast<BinaryWithFlagsSDNode>(N))
AddNodeIDFlags(ID, Node->getOpcode(), &Node->Flags);
/// AddBinaryNodeIDCustom - Add BinarySDNodes special infos
static void AddBinaryNodeIDCustom(FoldingSetNodeID &ID, unsigned Opcode,
bool nuw, bool nsw, bool exact) {
if (isBinOpWithFlags(Opcode))
AddBinaryNodeIDCustom(ID, nuw, nsw, exact);
}

static void AddNodeIDNode(FoldingSetNodeID &ID, unsigned short OpC,
Expand Down Expand Up @@ -509,6 +506,20 @@ static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) {
ID.AddInteger(ST->getPointerInfo().getAddrSpace());
break;
}
case ISD::SDIV:
case ISD::UDIV:
case ISD::SRA:
case ISD::SRL:
case ISD::MUL:
case ISD::ADD:
case ISD::SUB:
case ISD::SHL: {
const BinaryWithFlagsSDNode *BinNode = cast<BinaryWithFlagsSDNode>(N);
AddBinaryNodeIDCustom(
ID, N->getOpcode(), BinNode->Flags.hasNoUnsignedWrap(),
BinNode->Flags.hasNoSignedWrap(), BinNode->Flags.hasExact());
break;
}
case ISD::ATOMIC_CMP_SWAP:
case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
case ISD::ATOMIC_SWAP:
Expand Down Expand Up @@ -552,8 +563,6 @@ static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) {
}
} // end switch (N->getOpcode())

AddNodeIDFlags(ID, N);

// Target specific memory nodes could also have address spaces to check.
if (N->isTargetMemoryOpcode())
ID.AddInteger(cast<MemSDNode>(N)->getPointerInfo().getAddrSpace());
Expand Down Expand Up @@ -950,16 +959,14 @@ void SelectionDAG::allnodes_clear() {

BinarySDNode *SelectionDAG::GetBinarySDNode(unsigned Opcode, SDLoc DL,
SDVTList VTs, SDValue N1,
SDValue N2,
const SDNodeFlags *Flags) {
SDValue N2, bool nuw, bool nsw,
bool exact) {
if (isBinOpWithFlags(Opcode)) {
// If no flags were passed in, use a default flags object.
SDNodeFlags F;
if (Flags == nullptr)
Flags = &F;

BinaryWithFlagsSDNode *FN = new (NodeAllocator) BinaryWithFlagsSDNode(
Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs, N1, N2, *Flags);
Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs, N1, N2);
FN->Flags.setNoUnsignedWrap(nuw);
FN->Flags.setNoSignedWrap(nsw);
FN->Flags.setExact(exact);

return FN;
}
Expand Down Expand Up @@ -3229,7 +3236,7 @@ SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, SDLoc DL, EVT VT,
}

SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1,
SDValue N2, const SDNodeFlags *Flags) {
SDValue N2, bool nuw, bool nsw, bool exact) {
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
switch (Opcode) {
Expand Down Expand Up @@ -3693,20 +3700,22 @@ SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1,
// Memoize this node if possible.
BinarySDNode *N;
SDVTList VTs = getVTList(VT);
const bool BinOpHasFlags = isBinOpWithFlags(Opcode);
if (VT != MVT::Glue) {
SDValue Ops[] = {N1, N2};
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTs, Ops);
AddNodeIDFlags(ID, Opcode, Flags);
if (BinOpHasFlags)
AddBinaryNodeIDCustom(ID, Opcode, nuw, nsw, exact);
void *IP = nullptr;
if (SDNode *E = FindNodeOrInsertPos(ID, DL.getDebugLoc(), IP))
return SDValue(E, 0);

N = GetBinarySDNode(Opcode, DL, VTs, N1, N2, Flags);
N = GetBinarySDNode(Opcode, DL, VTs, N1, N2, nuw, nsw, exact);

CSEMap.InsertNode(N, IP);
} else {
N = GetBinarySDNode(Opcode, DL, VTs, N1, N2, Flags);
N = GetBinarySDNode(Opcode, DL, VTs, N1, N2, nuw, nsw, exact);
}

InsertNode(N);
Expand Down Expand Up @@ -6010,12 +6019,13 @@ SelectionDAG::getTargetInsertSubreg(int SRIdx, SDLoc DL, EVT VT,
/// getNodeIfExists - Get the specified node if it's already available, or
/// else return NULL.
SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList,
ArrayRef<SDValue> Ops,
const SDNodeFlags *Flags) {
ArrayRef<SDValue> Ops, bool nuw, bool nsw,
bool exact) {
if (VTList.VTs[VTList.NumVTs - 1] != MVT::Glue) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTList, Ops);
AddNodeIDFlags(ID, Opcode, Flags);
if (isBinOpWithFlags(Opcode))
AddBinaryNodeIDCustom(ID, nuw, nsw, exact);
void *IP = nullptr;
if (SDNode *E = FindNodeOrInsertPos(ID, DebugLoc(), IP))
return E;
Expand Down
24 changes: 4 additions & 20 deletions lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2139,8 +2139,6 @@ void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
bool nuw = false;
bool nsw = false;
bool exact = false;
FastMathFlags FMF;

if (const OverflowingBinaryOperator *OFBinOp =
dyn_cast<const OverflowingBinaryOperator>(&I)) {
nuw = OFBinOp->hasNoUnsignedWrap();
Expand All @@ -2149,20 +2147,9 @@ void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
if (const PossiblyExactOperator *ExactOp =
dyn_cast<const PossiblyExactOperator>(&I))
exact = ExactOp->isExact();
if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
FMF = FPOp->getFastMathFlags();

SDNodeFlags Flags;
Flags.setExact(exact);
Flags.setNoSignedWrap(nsw);
Flags.setNoUnsignedWrap(nuw);
Flags.setAllowReciprocal(FMF.allowReciprocal());
Flags.setNoInfs(FMF.noInfs());
Flags.setNoNaNs(FMF.noNaNs());
Flags.setNoSignedZeros(FMF.noSignedZeros());
Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());

SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
Op1, Op2, &Flags);
Op1, Op2, nuw, nsw, exact);
setValue(&I, BinNodeValue);
}

Expand Down Expand Up @@ -2210,12 +2197,9 @@ void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
dyn_cast<const PossiblyExactOperator>(&I))
exact = ExactOp->isExact();
}
SDNodeFlags Flags;
Flags.setExact(exact);
Flags.setNoSignedWrap(nsw);
Flags.setNoUnsignedWrap(nuw);

SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
&Flags);
nuw, nsw, exact);
setValue(&I, Res);
}

Expand Down
5 changes: 2 additions & 3 deletions lib/CodeGen/SelectionDAG/TargetLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2660,9 +2660,8 @@ SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
// TODO: For UDIV use SRL instead of SRA.
SDValue Amt =
DAG.getConstant(ShAmt, dl, getShiftAmountTy(Op1.getValueType()));
SDNodeFlags Flags;
Flags.setExact(true);
Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, &Flags);
Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, false, false,
true);
d = d.ashr(ShAmt);
}

Expand Down

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