Add an instruction selector emitter skeleton

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7629 91177308-0d34-0410-b5e6-96231b3b80d8
zoren · Aug 6, 2003 · 3f78134 · 3f78134
1 parent 0e5e49e
commit 3f78134
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Showing 2 changed files with 14 additions and 4 deletions.
diff --git a/support/tools/TableGen/TableGen.cpp b/support/tools/TableGen/TableGen.cpp
@@ -15,14 +15,15 @@
 #include "CodeEmitterGen.h"
 #include "RegisterInfoEmitter.h"
 #include "InstrInfoEmitter.h"
+#include "InstrSelectorEmitter.h"
 #include <algorithm>
 #include <fstream>
 
 enum ActionType {
   PrintRecords,
   GenEmitter,
   GenRegisterEnums, GenRegister, GenRegisterHeader,
-  GenInstrEnums, GenInstrs,
+  GenInstrEnums, GenInstrs, GenInstrSelector,
   PrintEnums,
   Parse,
 };
@@ -44,6 +45,8 @@ namespace {
                                "Generate enum values for instructions"),
                     clEnumValN(GenInstrs, "gen-instr-desc",
                                "Generate instruction descriptions"),
+                    clEnumValN(GenInstrSelector, "gen-instr-selector",
+                               "Generate an instruction selector"),
                     clEnumValN(PrintEnums, "print-enums",
                                "Print enum values for a class"),
                     clEnumValN(Parse, "parse",
@@ -440,7 +443,9 @@ int main(int argc, char **argv) {
     case GenInstrs:
       InstrInfoEmitter(Records).run(*Out);
       break;
-
+    case GenInstrSelector:
+      InstrSelectorEmitter(Records).run(*Out);
+      break;
     case PrintEnums:
       std::vector<Record*> Recs = Records.getAllDerivedDefinitions(Class);
       for (unsigned i = 0, e = Recs.size(); i != e; ++i)

diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp
@@ -15,14 +15,15 @@
 #include "CodeEmitterGen.h"
 #include "RegisterInfoEmitter.h"
 #include "InstrInfoEmitter.h"
+#include "InstrSelectorEmitter.h"
 #include <algorithm>
 #include <fstream>
 
 enum ActionType {
   PrintRecords,
   GenEmitter,
   GenRegisterEnums, GenRegister, GenRegisterHeader,
-  GenInstrEnums, GenInstrs,
+  GenInstrEnums, GenInstrs, GenInstrSelector,
   PrintEnums,
   Parse,
 };
@@ -44,6 +45,8 @@ namespace {
                                "Generate enum values for instructions"),
                     clEnumValN(GenInstrs, "gen-instr-desc",
                                "Generate instruction descriptions"),
+                    clEnumValN(GenInstrSelector, "gen-instr-selector",
+                               "Generate an instruction selector"),
                     clEnumValN(PrintEnums, "print-enums",
                                "Print enum values for a class"),
                     clEnumValN(Parse, "parse",
@@ -440,7 +443,9 @@ int main(int argc, char **argv) {
     case GenInstrs:
       InstrInfoEmitter(Records).run(*Out);
       break;
-
+    case GenInstrSelector:
+      InstrSelectorEmitter(Records).run(*Out);
+      break;
     case PrintEnums:
       std::vector<Record*> Recs = Records.getAllDerivedDefinitions(Class);
       for (unsigned i = 0, e = Recs.size(); i != e; ++i)