Skip to content

Commit

Permalink
Reapply r249121 : "[FastISel][x86] Teach how to select SSE2/AVX bitca…
Browse files Browse the repository at this point in the history 
…sts between 128/256-bit vector types."

This patch teaches FastIsel the following two things:
1) On SSE2, no instructions are needed for bitcasts between 128-bit vector types;
2) On AVX, no instructions are needed for bitcasts between 256-bit vector types.

Example:

  %1 = bitcast <4 x i31> %V to <2 x i64>

Before (-fast-isel -fast-isel-abort=1):

  FastIsel miss: %1 = bitcast <4 x i31> %V to <2 x i64>

Now we don't fall back to SelectionDAG and we correctly fold that computation
propagating the register associated to %V.

Originally reviewed here: http://reviews.llvm.org/D13347


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249147 91177308-0d34-0410-b5e6-96231b3b80d8
  • Loading branch information
@adibiagio
adibiagio committed Oct 2, 2015
1 parent 053f844 commit 93ccc33
Show file tree
Hide file tree
Showing 3 changed files with 513 additions and 0 deletions.
24 changes: 24 additions & 0 deletions lib/Target/X86/X86FastISel.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3234,6 +3234,30 @@ X86FastISel::fastSelectInstruction(const Instruction *I) {
updateValueMap(I, Reg);
return true;
}
case Instruction::BitCast: {
// Select SSE2/AVX bitcasts between 128/256 bit vector types.
if (!Subtarget->hasSSE2())
return false;

EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType());
EVT DstVT = TLI.getValueType(DL, I->getType());

if (!SrcVT.isSimple() || !DstVT.isSimple())
return false;

if (!SrcVT.is128BitVector() &&
!(Subtarget->hasAVX() && SrcVT.is256BitVector()))
return false;

unsigned Reg = getRegForValue(I->getOperand(0));
if (Reg == 0)
return false;

// No instruction is needed for conversion. Reuse the register used by
// the fist operand.
updateValueMap(I, Reg);
return true;
}
}

return false;
Expand Down
244 changes: 244 additions & 0 deletions test/CodeGen/X86/fast-isel-bitcasts-avx.ll
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,244 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx -fast-isel -fast-isel-abort=1 -asm-verbose=0 | FileCheck %s
;
; Bitcasts between 256-bit vector types are no-ops since no instruction is
; needed for the conversion.

define <4 x i64> @v8i32_to_v4i64(<8 x i32> %a) {
;CHECK-LABEL: v8i32_to_v4i64:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <8 x i32> %a to <4 x i64>
ret <4 x i64> %1
}

define <4 x i64> @v16i16_to_v4i64(<16 x i16> %a) {
;CHECK-LABEL: v16i16_to_v4i64:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <16 x i16> %a to <4 x i64>
ret <4 x i64> %1
}

define <4 x i64> @v32i8_to_v4i64(<32 x i8> %a) {
;CHECK-LABEL: v32i8_to_v4i64:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <32 x i8> %a to <4 x i64>
ret <4 x i64> %1
}

define <4 x i64> @v4f64_to_v4i64(<4 x double> %a) {
;CHECK-LABEL: v4f64_to_v4i64:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <4 x double> %a to <4 x i64>
ret <4 x i64> %1
}

define <4 x i64> @v8f32_to_v4i64(<8 x float> %a) {
;CHECK-LABEL: v8f32_to_v4i64:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <8 x float> %a to <4 x i64>
ret <4 x i64> %1
}

define <8 x i32> @v4i64_to_v8i32(<4 x i64> %a) {
;CHECK-LABEL: v4i64_to_v8i32:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <4 x i64> %a to <8 x i32>
ret <8 x i32> %1
}

define <8 x i32> @v16i16_to_v8i32(<16 x i16> %a) {
;CHECK-LABEL: v16i16_to_v8i32:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <16 x i16> %a to <8 x i32>
ret <8 x i32> %1
}

define <8 x i32> @v32i8_to_v8i32(<32 x i8> %a) {
;CHECK-LABEL: v32i8_to_v8i32:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <32 x i8> %a to <8 x i32>
ret <8 x i32> %1
}

define <8 x i32> @v4f64_to_v8i32(<4 x double> %a) {
;CHECK-LABEL: v4f64_to_v8i32:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <4 x double> %a to <8 x i32>
ret <8 x i32> %1
}

define <8 x i32> @v8f32_to_v8i32(<8 x float> %a) {
;CHECK-LABEL: v8f32_to_v8i32:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <8 x float> %a to <8 x i32>
ret <8 x i32> %1
}

define <16 x i16> @v4i64_to_v16i16(<4 x i64> %a) {
;CHECK-LABEL: v4i64_to_v16i16:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <4 x i64> %a to <16 x i16>
ret <16 x i16> %1
}

define <16 x i16> @v8i32_to_v16i16(<8 x i32> %a) {
;CHECK-LABEL: v8i32_to_v16i16:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <8 x i32> %a to <16 x i16>
ret <16 x i16> %1
}

define <16 x i16> @v32i8_to_v16i16(<32 x i8> %a) {
;CHECK-LABEL: v32i8_to_v16i16:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <32 x i8> %a to <16 x i16>
ret <16 x i16> %1
}

define <16 x i16> @v4f64_to_v16i16(<4 x double> %a) {
;CHECK-LABEL: v4f64_to_v16i16:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <4 x double> %a to <16 x i16>
ret <16 x i16> %1
}

define <16 x i16> @v8f32_to_v16i16(<8 x float> %a) {
;CHECK-LABEL: v8f32_to_v16i16:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <8 x float> %a to <16 x i16>
ret <16 x i16> %1
}

define <32 x i8> @v16i16_to_v32i8(<16 x i16> %a) {
;CHECK-LABEL: v16i16_to_v32i8:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <16 x i16> %a to <32 x i8>
ret <32 x i8> %1
}

define <32 x i8> @v4i64_to_v32i8(<4 x i64> %a) {
;CHECK-LABEL: v4i64_to_v32i8:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <4 x i64> %a to <32 x i8>
ret <32 x i8> %1
}

define <32 x i8> @v8i32_to_v32i8(<8 x i32> %a) {
;CHECK-LABEL: v8i32_to_v32i8:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <8 x i32> %a to <32 x i8>
ret <32 x i8> %1
}

define <32 x i8> @v4f64_to_v32i8(<4 x double> %a) {
;CHECK-LABEL: v4f64_to_v32i8:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <4 x double> %a to <32 x i8>
ret <32 x i8> %1
}

define <32 x i8> @v8f32_to_v32i8(<8 x float> %a) {
;CHECK-LABEL: v8f32_to_v32i8:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <8 x float> %a to <32 x i8>
ret <32 x i8> %1
}

define <8 x float> @v32i8_to_v8f32(<32 x i8> %a) {
;CHECK-LABEL: v32i8_to_v8f32:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <32 x i8> %a to <8 x float>
ret <8 x float> %1
}

define <8 x float> @v16i16_to_v8f32(<16 x i16> %a) {
;CHECK-LABEL: v16i16_to_v8f32:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <16 x i16> %a to <8 x float>
ret <8 x float> %1
}

define <8 x float> @v4i64_to_v8f32(<4 x i64> %a) {
;CHECK-LABEL: v4i64_to_v8f32:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <4 x i64> %a to <8 x float>
ret <8 x float> %1
}

define <8 x float> @v8i32_to_v8f32(<8 x i32> %a) {
;CHECK-LABEL: v8i32_to_v8f32:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <8 x i32> %a to <8 x float>
ret <8 x float> %1
}

define <8 x float> @v4f64_to_v8f32(<4 x double> %a) {
;CHECK-LABEL: v4f64_to_v8f32:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <4 x double> %a to <8 x float>
ret <8 x float> %1
}

define <4 x double> @v8f32_to_v4f64(<8 x float> %a) {
;CHECK-LABEL: v8f32_to_v4f64:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <8 x float> %a to <4 x double>
ret <4 x double> %1
}

define <4 x double> @v32i8_to_v4f64(<32 x i8> %a) {
;CHECK-LABEL: v32i8_to_v4f64:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <32 x i8> %a to <4 x double>
ret <4 x double> %1
}

define <4 x double> @v16i16_to_v4f64(<16 x i16> %a) {
;CHECK-LABEL: v16i16_to_v4f64:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <16 x i16> %a to <4 x double>
ret <4 x double> %1
}

define <4 x double> @v4i64_to_v4f64(<4 x i64> %a) {
;CHECK-LABEL: v4i64_to_v4f64:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <4 x i64> %a to <4 x double>
ret <4 x double> %1
}

define <4 x double> @v8i32_to_v4f64(<8 x i32> %a) {
;CHECK-LABEL: v8i32_to_v4f64:
;CHECK-NEXT: .cfi_startproc
;CHECK-NEXT: ret
%1 = bitcast <8 x i32> %a to <4 x double>
ret <4 x double> %1
}
Loading

0 comments on commit 93ccc33

Please sign in to comment.