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Merge branch 'clk-fixes' into clk-next
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* clk-fixes:
  clk: efm32gg: Pass correct type to hw provider registration
  clk: berlin: Pass correct type to hw provider registration
  clk: sunxi: Fix M factor computation for APB1
  clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parent
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bebarino committed Nov 16, 2016
2 parents 9a881bc + c861667 commit 977f0ab
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Showing 5 changed files with 16 additions and 4 deletions.
2 changes: 1 addition & 1 deletion drivers/clk/berlin/bg2.c
Original file line number Diff line number Diff line change
Expand Up @@ -685,7 +685,7 @@ static void __init berlin2_clock_setup(struct device_node *np)
}

/* register clk-provider */
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data);
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);

return;

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2 changes: 1 addition & 1 deletion drivers/clk/berlin/bg2q.c
Original file line number Diff line number Diff line change
Expand Up @@ -382,7 +382,7 @@ static void __init berlin2q_clock_setup(struct device_node *np)
}

/* register clk-provider */
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data);
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);

return;

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2 changes: 1 addition & 1 deletion drivers/clk/clk-efm32gg.c
Original file line number Diff line number Diff line change
Expand Up @@ -82,6 +82,6 @@ static void __init efm32gg_cmu_init(struct device_node *np)
hws[clk_HFPERCLKDAC0] = clk_hw_register_gate(NULL, "HFPERCLK.DAC0",
"HFXO", 0, base + CMU_HFPERCLKEN0, 17, 0, NULL);

of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data);
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
}
CLK_OF_DECLARE(efm32ggcmu, "efm32gg,cmu", efm32gg_cmu_init);
12 changes: 12 additions & 0 deletions drivers/clk/sunxi-ng/ccu-sun6i-a31.c
Original file line number Diff line number Diff line change
Expand Up @@ -191,6 +191,8 @@ static struct clk_div_table axi_div_table[] = {
static SUNXI_CCU_DIV_TABLE(axi_clk, "axi", "cpu",
0x050, 0, 3, axi_div_table, 0);

#define SUN6I_A31_AHB1_REG 0x054

static const char * const ahb1_parents[] = { "osc32k", "osc24M",
"axi", "pll-periph" };

Expand Down Expand Up @@ -1230,6 +1232,16 @@ static void __init sun6i_a31_ccu_setup(struct device_node *node)
val &= BIT(16);
writel(val, reg + SUN6I_A31_PLL_MIPI_REG);

/* Force AHB1 to PLL6 / 3 */
val = readl(reg + SUN6I_A31_AHB1_REG);
/* set PLL6 pre-div = 3 */
val &= ~GENMASK(7, 6);
val |= 0x2 << 6;
/* select PLL6 / pre-div */
val &= ~GENMASK(13, 12);
val |= 0x3 << 12;
writel(val, reg + SUN6I_A31_AHB1_REG);

sunxi_ccu_probe(node, reg, &sun6i_a31_ccu_desc);

ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
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2 changes: 1 addition & 1 deletion drivers/clk/sunxi/clk-sunxi.c
Original file line number Diff line number Diff line change
Expand Up @@ -373,7 +373,7 @@ static void sun4i_get_apb1_factors(struct factors_request *req)
else
calcp = 3;

calcm = (req->parent_rate >> calcp) - 1;
calcm = (div >> calcp) - 1;

req->rate = (req->parent_rate >> calcp) / (calcm + 1);
req->m = calcm;
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