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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upst…
…ream-linus Pull MIPS updates from Ralf Baechle: "These are the highlists of the main MIPS pull request for 4.4: - Add latencytop support - Support appended DTBs - VDSO support and initially use it for gettimeofday. - Drop the .MIPS.abiflags and ELF NOTE sections from vmlinux - Support for the 5KE, an internal test core. - Switch all MIPS platfroms to libata drivers. - Improved support, cleanups for ralink and Lantiq platforms. - Support for the new xilfpga platform. - A number of DTB improvments for BMIPS. - Improved support for CM and CPS. - Minor JZ4740 and BCM47xx enhancements" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (120 commits) MIPS: idle: add case for CPU_5KE MIPS: Octeon: Support APPENDED_DTB MIPS: vmlinux: create a section for appended DTB MIPS: Clean up compat_siginfo_t MIPS: Fix PAGE_MASK definition MIPS: BMIPS: Enable GZIP ramdisk and timed printks MIPS: Add xilfpga defconfig MIPS: xilfpga: Add mipsfpga platform code MIPS: xilfpga: Add xilfpga device tree files. dt-bindings: MIPS: Document xilfpga bindings and boot style MIPS: Make MIPS_CMDLINE_DTB default MIPS: Make the kernel arguments from dtb available MIPS: Use USE_OF as the guard for appended dtb MIPS: BCM63XX: Use pr_* instead of printk MIPS: Loongson: Cleanup CONFIG_LOONGSON_SUSPEND. MIPS: lantiq: Disable xbar fpi burst mode MIPS: lantiq: Force the crossbar to big endian MIPS: lantiq: Initialize the USB core on boot MIPS: lantiq: Return correct value for fpi clock on ar9 MIPS: ralink: Add missing clock on rt305x ...
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Imagination University Program MIPSfpga | ||
======================================= | ||
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Under the Imagination University Program, a microAptiv UP core has been | ||
released for academic usage. | ||
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As we are dealing with a MIPS core instantiated on an FPGA, specifications | ||
are fluid and can be varied in RTL. | ||
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This binding document is provided as baseline guidance for the example | ||
project provided by IMG. | ||
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The example project runs on the Nexys4DDR board by Digilent powered by | ||
the ARTIX-7 FPGA by Xilinx. | ||
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Relevant details about the example project and the Nexys4DDR board: | ||
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- microAptiv UP core m14Kc | ||
- 50MHz clock speed | ||
- 128Mbyte DDR RAM at 0x0000_0000 | ||
- 8Kbyte RAM at 0x1000_0000 | ||
- axi_intc at 0x1020_0000 | ||
- axi_uart16550 at 0x1040_0000 | ||
- axi_gpio at 0x1060_0000 | ||
- axi_i2c at 0x10A0_0000 | ||
- custom_gpio at 0x10C0_0000 | ||
- axi_ethernetlite at 0x10E0_0000 | ||
- 8Kbyte BootRAM at 0x1FC0_0000 | ||
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Required properties: | ||
-------------------- | ||
- compatible: Must include "digilent,nexys4ddr","img,xilfpga". | ||
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CPU nodes: | ||
---------- | ||
A "cpus" node is required. Required properties: | ||
- #address-cells: Must be 1. | ||
- #size-cells: Must be 0. | ||
A CPU sub-node is also required for at least CPU 0. Required properties: | ||
- device_type: Must be "cpu". | ||
- compatible: Must be "mips,m14Kc". | ||
- reg: Must be <0>. | ||
- clocks: phandle to ext clock for fixed-clock received by MIPS core. | ||
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Example: | ||
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compatible = "img,xilfpga","digilent,nexys4ddr"; | ||
cpus { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
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cpu0: cpu@0 { | ||
device_type = "cpu"; | ||
compatible = "mips,m14Kc"; | ||
reg = <0>; | ||
clocks = <&ext>; | ||
}; | ||
}; | ||
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ext: ext { | ||
compatible = "fixed-clock"; | ||
#clock-cells = <0>; | ||
clock-frequency = <50000000>; | ||
}; | ||
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Boot protocol: | ||
-------------- | ||
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The BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000. | ||
This is for easy reprogrammibility via JTAG. | ||
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The BootRAM initializes the cache and the axi_uart peripheral. | ||
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DDR initialization is already handled by a HW IP block. | ||
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When the example project bitstream is loaded, the cpu_reset button | ||
needs to be pressed. | ||
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The bootram initializes the cache and axi_uart. | ||
Then outputs MIPSFPGA\n\r on the serial port on the Nexys4DDR board. | ||
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At this point, the board is ready to load the Linux kernel | ||
vmlinux file via JTAG. |
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