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| C:\Documents and Settings\ex9\ex4_t.ngc 1429355511 | ||
| OK |
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| <?xml version="1.0" encoding="UTF-8"?> | ||
| <!-- IMPORTANT: This is an internal file that has been generated | ||
| by the Xilinx ISE software. Any direct editing or | ||
| changes made to this file may result in unpredictable | ||
| behavior or data corruption. It is strongly advised that | ||
| users do not edit the contents of this file. --> | ||
| <messages> | ||
| </messages> | ||
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| <?xml version="1.0" encoding="UTF-8"?> | ||
| <!-- IMPORTANT: This is an internal file that has been generated | ||
| by the Xilinx ISE software. Any direct editing or | ||
| changes made to this file may result in unpredictable | ||
| behavior or data corruption. It is strongly advised that | ||
| users do not edit the contents of this file. --> | ||
| <messages> | ||
| <msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set. | ||
| </msg> | ||
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| <msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. | ||
| </msg> | ||
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| </messages> | ||
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| <?xml version="1.0" encoding="UTF-8"?> | ||
| <!-- IMPORTANT: This is an internal file that has been generated | ||
| by the Xilinx ISE software. Any direct editing or | ||
| changes made to this file may result in unpredictable | ||
| behavior or data corruption. It is strongly advised that | ||
| users do not edit the contents of this file. --> | ||
| <messages> | ||
| </messages> | ||
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| @@ -0,0 +1,14 @@ | ||
| <?xml version="1.0" encoding="UTF-8"?> | ||
| <!-- IMPORTANT: This is an internal file that has been generated | ||
| by the Xilinx ISE software. Any direct editing or | ||
| changes made to this file may result in unpredictable | ||
| behavior or data corruption. It is strongly advised that | ||
| users do not edit the contents of this file. --> | ||
| <messages> | ||
| <msg type="info" file="Par" num="282" delta="old" >No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". | ||
| </msg> | ||
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| <msg type="info" file="Timing" num="2761" delta="old" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg> | ||
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| </messages> | ||
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| @@ -0,0 +1,15 @@ | ||
| <?xml version="1.0" encoding="UTF-8"?> | ||
| <!-- IMPORTANT: This is an internal file that has been generated --> | ||
| <!-- by the Xilinx ISE software. Any direct editing or --> | ||
| <!-- changes made to this file may result in unpredictable --> | ||
| <!-- behavior or data corruption. It is strongly advised that --> | ||
| <!-- users do not edit the contents of this file. --> | ||
| <!-- --> | ||
| <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> | ||
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| <messages> | ||
| <msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file "C:/Documents and Settings/ex9/ex9.v" into library work</arg> | ||
| </msg> | ||
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| </messages> | ||
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| @@ -0,0 +1,21 @@ | ||
| <?xml version="1.0" encoding="UTF-8"?> | ||
| <!-- IMPORTANT: This is an internal file that has been generated | ||
| by the Xilinx ISE software. Any direct editing or | ||
| changes made to this file may result in unpredictable | ||
| behavior or data corruption. It is strongly advised that | ||
| users do not edit the contents of this file. --> | ||
| <messages> | ||
| <msg type="info" file="Timing" num="2698" delta="old" >No timing constraints found, doing default enumeration.</msg> | ||
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| <msg type="info" file="Timing" num="3412" delta="old" >To improve timing, see the Timing Closure User Guide (UG612).</msg> | ||
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| <msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg> | ||
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| <msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg> | ||
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| <msg type="info" file="Timing" num="3390" delta="old" >This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.</msg> | ||
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| <msg type="info" file="Timing" num="3389" delta="old" >This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.</msg> | ||
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| </messages> | ||
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| @@ -0,0 +1,60 @@ | ||
| <?xml version="1.0" encoding="UTF-8"?> | ||
| <!-- IMPORTANT: This is an internal file that has been generated | ||
| by the Xilinx ISE software. Any direct editing or | ||
| changes made to this file may result in unpredictable | ||
| behavior or data corruption. It is strongly advised that | ||
| users do not edit the contents of this file. --> | ||
| <messages> | ||
| <msg type="warning" file="Xst" num="1780" delta="old" >Signal <<arg fmt="%s" index="1">t<16></arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process. | ||
| </msg> | ||
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| <msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">t_15</arg>> in Unit <<arg fmt="%s" index="2">ex4_t</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><answer4_3> </arg> | ||
| </msg> | ||
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| <msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">t_14</arg>> in Unit <<arg fmt="%s" index="2">ex4_t</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><answer4_2> </arg> | ||
| </msg> | ||
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| <msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">t_13</arg>> in Unit <<arg fmt="%s" index="2">ex4_t</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><answer4_1> </arg> | ||
| </msg> | ||
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| <msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">t_12</arg>> in Unit <<arg fmt="%s" index="2">ex4_t</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><answer4_0> </arg> | ||
| </msg> | ||
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| <msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">t_11</arg>> in Unit <<arg fmt="%s" index="2">ex4_t</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><answer3_3> </arg> | ||
| </msg> | ||
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| <msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">t_10</arg>> in Unit <<arg fmt="%s" index="2">ex4_t</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><answer3_2> </arg> | ||
| </msg> | ||
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| <msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">t_9</arg>> in Unit <<arg fmt="%s" index="2">ex4_t</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><answer3_1> </arg> | ||
| </msg> | ||
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| <msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">t_8</arg>> in Unit <<arg fmt="%s" index="2">ex4_t</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><answer3_0> </arg> | ||
| </msg> | ||
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| <msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">t_3</arg>> in Unit <<arg fmt="%s" index="2">ex4_t</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><answer1_3> </arg> | ||
| </msg> | ||
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| <msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">t_2</arg>> in Unit <<arg fmt="%s" index="2">ex4_t</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><answer1_2> </arg> | ||
| </msg> | ||
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| <msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">t_1</arg>> in Unit <<arg fmt="%s" index="2">ex4_t</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><answer1_1> </arg> | ||
| </msg> | ||
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| <msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">t_0</arg>> in Unit <<arg fmt="%s" index="2">ex4_t</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><answer1_0> </arg> | ||
| </msg> | ||
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| <msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">t_7</arg>> in Unit <<arg fmt="%s" index="2">ex4_t</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><answer2_3> </arg> | ||
| </msg> | ||
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| <msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">t_6</arg>> in Unit <<arg fmt="%s" index="2">ex4_t</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><answer2_2> </arg> | ||
| </msg> | ||
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| <msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">t_5</arg>> in Unit <<arg fmt="%s" index="2">ex4_t</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><answer2_1> </arg> | ||
| </msg> | ||
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| <msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">t_4</arg>> in Unit <<arg fmt="%s" index="2">ex4_t</arg>> is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4"><answer2_0> </arg> | ||
| </msg> | ||
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| </messages> | ||
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