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Repository for future projects that want to use the CEU

SystemVerilog 1 2 Updated Oct 23, 2019

A camera ISP (image signal processor) pipeline that contains modules with simple to complex algorithms implemented at the application level.

Python 165 44 Updated Sep 4, 2024

Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.

Python 1,509 639 Updated Sep 12, 2024
Verilog 84 39 Updated Dec 23, 2016

Image Signal Processor

Python 1,149 414 Updated Feb 1, 2023

Image Signal Processing (ISP) Guide. Learn all about the process of converting an image/video into digital form by performing tasks like noise reduction, filtering, auto exposure, autofocus, HDR co…

Python 422 85 Updated Jan 4, 2024

xk265:HEVC/H.265 Video Encoder IP Core (RTL)

Verilog 237 78 Updated Apr 9, 2023

xkISP:Xinkai ISP IP Core (HLS)

Verilog 255 106 Updated Mar 14, 2023