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A 32-bit 7-stage RISC-V pipeline CPU with traps, virtual memory, S privilege mode, cache, branch prediction and TLB. Supports VGA, flash and uCore (a simple OS). Course project of "Computer Organization and Design" (2023), Tsinghua University.
CHEN-Xinsheng/cod23-grp19
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A 32-bit 7-stage RISC-V pipeline CPU with traps, virtual memory, S privilege mode, cache, branch prediction and TLB. Supports VGA, flash and uCore (a simple OS). Course project of "Computer Organization and Design" (2023), Tsinghua University.
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