Streaming video over USB 3.0 using MAX10 FPGA and CYUSB3014 synchronous slave mode.
Video:
____________________________________
| FPGA |
______ | ________ __________ | ___________
| | | | CAMERA | | MAIN FSM | | | |
|CAMERA|----->| CAPTURE|<--->| & FIFO |<---------->| CYUSB3014 |
|______| | -------- ---------- | |___________|
^ | ________ | |
| | | CAMERA | | |
----------| CONFIG | | |
| -------- | |
| Pixel clock | USB clock |
| domain | domain |
|______________________|_____________|
Top level module parameters define image resolution, color mode (grayscale or RGB565), camera I2C address and camera registers memory init file.
| Parameter | Description |
|---|---|
| IM_X | Image width |
| IM_Y | Image height |
| COLOR_MODE | 1 - Grayscale, 2 - RGB565 |
| FPGA_PROCESSING | 1 - Convert RGB565 -> 8-bit Grayscale, 2 - No processing |
| CAMERA_ADDR | Camera I2C address |
| MIF_FILE | Camera registers memory init file |
| FAST_SIM | 0 - Normal mode, 1 - Fast sim mode, skip camera initialization |
The camera configuration module initializes camera registers based on mif file and I2C address.
When configuration is done and start_stream signal set by the main FSM, the module waits for VSYNC falling edge and then captures pixel data from the camera by parallel DVP interface. If grayscale mode has been selected, the module converts RGB565 -> RGB888 -> 8-bit grayscale using simple pipeline. Otherwise, pixel data is written straight to the FIFO.
The main FSM module handles the following commands from the PC:
| Command | Description |
|---|---|
| 0x0101 | Get image parameters |
| 0x1111 | Start video stream |
| 0x0f0f | Stop video stream |
After receiving the get image parameters command, a six-byte image parameters packet will be sent to the PC.
| Byte | Parameter | Description |
|---|---|---|
| 0 | IM_TYPE | Grayscale - 0xAA, RGB565 - 0xBB |
| 1 | NONE | Reserved |
| 2-3 | IM_X | Image width |
| 4-5 | IM_Y | Image height |
This design is based on the ARROW DECA, Cypress CYUSB3KIT-003 development kit and OV5642 camera module.
This design uses CYUSB3014 synchronous slave mode with a 16-bit data bus. The clock signal is generated by the CYUSB3014. Two auto DMA channels are used to move data. The FX3 SDK is required to build the firmware.
| DMA Channel | DMA buffer size | DMA buffer count |
|---|---|---|
| USB -> FPGA | 1024 bytes | 1 |
| FPGA -> USB | 16384 bytes | 4 |
Simple python-based client are included.
Tested on Ubuntu linux and Windows 10 (WinUSB driver).
Dependencies: Python 3.7+, NumPy, OpenCV, libusb-1.0, python-libusb1