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PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory techniques. Prototype on a RISC-V rocket chip system impleme…

59 8 Updated Dec 11, 2023

HWASim is a simulator for heterogeneous systems with CPUs and Hardware Accelerators (HWAs). It is released with the DASH memory scheduler paper that appeared at ACM TACO 2016: https://users.ece.cmu…

C# 17 3 Updated Jan 11, 2016

A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the…

C++ 595 209 Updated Aug 29, 2023

SystemVerilog extension for Visual Studio Code

JavaScript 12 3 Updated Dec 18, 2018

Generator Bootcamp Material: Learn Chisel the Right Way

Jupyter Notebook 990 280 Updated Sep 10, 2024

educational microarchitectures for risc-v isa

Scala 65 21 Updated Feb 18, 2019

A High-performance Timing Analysis Tool for VLSI Systems

Verilog 577 144 Updated May 26, 2023

Verilog AXI stream components for FPGA implementation

Python 753 230 Updated Aug 7, 2024

A Powerful & Elegant vimrc

Vim Script 1 1 Updated Aug 8, 2017

Experiments with fixed function renderers and Chisel HDL

Scala 59 10 Updated Mar 31, 2019

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

Scala 208 36 Updated Jan 23, 2020

Rocket Chip Generator

Scala 3,292 1,138 Updated Dec 3, 2024

Verilog coding style examples

Verilog 3 1 Updated Jul 11, 2013

An open-source static random access memory (SRAM) compiler.

Python 847 205 Updated Nov 14, 2024

180+ Algorithm & Data Structure Problems using C++

C++ 5,959 1,324 Updated Feb 6, 2024

Simple but cute and helpful bash settings

Shell 152 79 Updated Jun 7, 2021

RTL, Cmodel, and testbench for NVDLA

Verilog 1,765 572 Updated Mar 2, 2022