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Commits on Dec 27, 2017

• Use old C style comments. (riscv#18)

  Show description for 25881d8
  

  timsifive

  authored and

  aswaterman

  committed
  25881d8

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Commits on Nov 27, 2017

• Rename sptbr to satp and sbadaddr to stval

  Show description for 7c3db43
  aswaterman

  committed
  7c3db43

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Commits on May 8, 2017

• Add UXl/SXL

  aswaterman

  committed
  1ac9833

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Commits on Mar 30, 2017

• New PMP encoding

  aswaterman

  committed
  e4c9357

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Commits on Mar 27, 2017

• Separate page faults from physical memory access exceptions

  aswaterman

  committed
  d86c50a

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Commits on Mar 23, 2017

• Add PMP

  aswaterman

  committed
  771cd8a

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• Add TW/TVM/TSR fields to mstatus

  aswaterman

  committed
  ec5a822

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Commits on Mar 9, 2017

• Update SPTBR fields

  aswaterman

  committed
  b6747a2

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Commits on Feb 21, 2017

• Use gcc csr register constraint

  aswaterman

  committed
  282321b

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• Drop mstatus.VM field

  aswaterman

  committed
  689c591

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Commits on Feb 8, 2017

• Encode VM type in sptbr, not mstatus

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  aswaterman

  committed
  cd10c71

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Commits on Dec 7, 2016

• avoid non-standard predefined macros

  aswaterman

  committed
  7650b39

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Commits on Aug 27, 2016

• Add mcontrol type constants. (riscv#11)

  

  timsifive

  authored and

  aswaterman

  committed
  9f3e389

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Commits on Aug 25, 2016

• Make hardware triggers match latest spec.

  

  timsifive

  authored and

  Andrew Waterman

  committed
  1a25601

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Commits on Jul 6, 2016

• Update to new PTE format

  

  Andrew Waterman

  committed
  16c63f3

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Commits on Jun 10, 2016

• Update breakpoint spec

  

  Andrew Waterman

  committed
  e9f43f8

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Commits on Jun 9, 2016

• Add breakpoint CSRs

  

  Andrew Waterman

  committed
  56696c7

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Commits on Jun 3, 2016

• Keep DCSR_XDEBUGVER unsigned.

  timsifive

  committed
  8a441f9

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Commits on Jun 1, 2016

• Add dret instruction and debug CSRs. (riscv#5)

  

  timsifive

  authored and

  aswaterman

  committed
  1783043

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Commits on May 14, 2016

• Rename "Device Interrupt" to "External Interrupt"

  

  Andrew Waterman

  committed
  e9eb2c4

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Commits on May 1, 2016

• Remove mcfgaddr; change memory map

  

  Andrew Waterman

  committed
  af5e124

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Commits on Mar 10, 2016

• Allow immediates for write_csr; check for signedness

  

  Andrew Waterman

  committed
  fee20f1

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Commits on Mar 4, 2016

• Update CSR encoding

  

  Andrew Waterman

  committed
  080ec44

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Commits on Feb 29, 2016

• WIP on priv spec v1.9

  

  Andrew Waterman

  committed
  9b7dce6

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Commits on Feb 6, 2016

• WIP on priv spec v1.9

  

  Andrew Waterman

  committed
  baed881

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Commits on May 14, 2015

• Fix VM, MIP encoding

  

  Andrew Waterman

  committed
  c177bd3

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Commits on May 9, 2015

• Update to privileged architecture version 1.7

  

  Andrew Waterman

  committed
  fc8ac29

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Commits on Apr 2, 2015

• Distinguish Sv39/Sv48; reserve some PPN bits

  

  Andrew Waterman

  committed
  8052925

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Commits on Mar 24, 2015

• New virtual memory implementation (Sv39)

  

  Andrew Waterman

  committed
  9983d49

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Commits on Mar 13, 2015

• Add referenced/dirty bits to PTE

  

  Andrew Waterman

  committed
  07ad8b6

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• Update to new privileged spec

  

  Andrew Waterman

  committed
  43ca48c

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Commits on Feb 6, 2014

• Reserve 16 uarch-specific read-only userspace counters

  aswaterman

  committed
  2cc2860

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Commits on Jan 21, 2014

• Auto-generate exception cause numbers

  aswaterman

  committed
  1b4f2b1

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Commits on Nov 25, 2013

• New privileged ISA

  aswaterman

  committed
  2d11bac

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