Popular repositories Loading

1. register-maps register-maps Public

   Forked from NJDFan/register-maps

   Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.

   Python

2. RegRTLGen RegRTLGen Public

   Forked from nguyenquanicd/RegRTLGen

   This is the open source tool which is used to create the System Verilog RTL code of register module

   Python

3. EECE490_embedded-soc EECE490_embedded-soc Public

   Forked from lootr5858/EECE490_embedded-soc

   Embedded SOC course with Cortex M0 & Verilog HDL

   Verilog

4. BR_SW_L BR_SW_L Public

   Forked from lisunhua/BR_SW_L

   Test Codes

   C

5. hw hw Public

   Forked from nvdla/hw

   RTL, Cmodel, and testbench for NVDLA

   Verilog

6. SweRV-FPU SweRV-FPU Public

   Forked from Wishah-Naseer/SweRV-FPU

   SweRV-EL2 Core with Floating Point Support

   SystemVerilog