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Cores-VeeR-EL2 Public
Forked from chipsalliance/Cores-VeeR-EL2VeeR EL2 Core
SystemVerilog Apache License 2.0 UpdatedJun 5, 2024 -
VeeRwolf Public
Forked from chipsalliance/VeeRwolfFuseSoC-based SoC for VeeR EH1 and EL2
Verilog UpdatedMay 25, 2024 -
SweRV-FPU Public
Forked from Wishah-Naseer/SweRV-FPUSweRV-EL2 Core with Floating Point Support
SystemVerilog UpdatedJul 16, 2022 -
caravel-swerv-el2 Public
Forked from chipsalliance/caravel-swerv-el2Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
Verilog Apache License 2.0 UpdatedDec 16, 2020 -
RegRTLGen Public
Forked from nguyenquanicd/RegRTLGenThis is the open source tool which is used to create the System Verilog RTL code of register module
Python UpdatedOct 24, 2020 -
EECE490_embedded-soc Public
Forked from lootr5858/EECE490_embedded-socEmbedded SOC course with Cortex M0 & Verilog HDL
Verilog UpdatedSep 26, 2020 -
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RTL, Cmodel, and testbench for NVDLA
Verilog Other UpdatedOct 17, 2019 -
register-maps Public
Forked from NJDFan/register-mapsUse XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.
Python GNU General Public License v3.0 UpdatedJul 3, 2019