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Commits on May 17, 2018

• [RISCV] Add support for .half, .hword, .word, .dword directives

  Show description for d2427ff
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  committed
  d2427ff

Commits on May 11, 2018

• [RISCV] Support .option rvc and norvc assembler directives

  Show description for 0d10241
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  0d10241

Commits on Apr 27, 2018

• [RISCV] Add remat.ll test case

  Show description for 38ee805
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  38ee805

Commits on Apr 26, 2018

• [RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot

  Show description for 72eae93
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  72eae93

• [RISCV] Implement isZextFree

  Show description for cdb6162
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  cdb6162

• [RISCV] Add test case showing suboptimal codegen when loading unsigned char/short

  Show description for 0faf8b4
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  0faf8b4

• [RISCV] Implement isTruncateFree

  Show description for 9ead1e2
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  9ead1e2

• [RISCV] Implement isLegalICmpImmediate

  Show description for 22648be
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  22648be

• [RISCV] Implement isLegalAddImmediate

  Show description for e79c730
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  e79c730

• [RISCV] Add test/CodeGen/RISCV/lsr-legaladdimm.ll

  Show description for 3797a2a
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  3797a2a

• [RISCV] Implement isLegalAddressingMode for RISC-V

  Show description for bc5698b
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  bc5698b

Commits on Apr 25, 2018

• [RISCV] Allow call pseudoinstruction to be used to call a function name that coincides with a register name

  Show description for a96f6b8
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  a96f6b8

Commits on Apr 18, 2018

• [RISCV] Add test changes missed from rL330293

  Show description for 4b5e638
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  4b5e638

• [RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bits

  Show description for e50f577
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  e50f577

• [RISCV] Add imm-cse.ll test case

  Show description for 54ecebc
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  54ecebc

• [RISCV] Expand codegen -> compression sanity checks and move to a single file

  Show description for 6663e67
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  6663e67

• Revert "[RISCV] implement li pseudo instruction"

  Show description for eea8107
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  eea8107

• [RISCV] Add specific tests for materialising imm32hi20 constants

  Show description for c947c65
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  c947c65

Commits on Apr 17, 2018

• [RISCV] implement li pseudo instruction

  Show description for 6b11f68
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  committed
  6b11f68

Commits on Apr 12, 2018

• [RISCV] Codegen support for RV32D floating point comparison operations

  Show description for 14efaa1
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  14efaa1

• [RISCV] Codegen support for RV32D floating point conversion operations

  Show description for bbb41d8
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  bbb41d8

• [RISCV] Add codegen support for RV32D floating point arithmetic operations

  Show description for 3664487
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  3664487

• [RISCV] Add tests missed in r329871

  Show description for 0cc09b8
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  committed
  0cc09b8

• [RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling conv

  Show description for 633653d
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  committed
  633653d

Commits on Mar 21, 2018

• [RISCV] Codegen support for RV32F floating point comparison operations

  Show description for 94f16be
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  committed
  94f16be

• [RISCV] Add tests missed from r327979

  Show description for 30a32a6
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  30a32a6

Commits on Mar 20, 2018

• [RISCV] Add codegen for RV32F floating point load/store

  Show description for 8ce26eb
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  committed
  8ce26eb

• [RISCV] Add codegen for RV32F arithmetic and conversion operations

  Show description for a07f460
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  a07f460

Commits on Mar 19, 2018

• [RISCV] Peephole optimisation for load/store of global values or constant addresses

  Show description for abb819e
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  abb819e

Commits on Feb 28, 2018

• [RISCV] Update two tests after r326208

  Show description for 58f8c5d
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  58f8c5d

Commits on Feb 22, 2018

• [RISCV][NFC] Make logic in RISCVMCCodeEmitter::getImmOpValue more defensive

  Show description for 2f5aa68
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  2f5aa68

Commits on Feb 17, 2018

• [RISCV] Revert r324172 now r323991 was reverted

  Show description for b10600e
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  b10600e

Commits on Feb 3, 2018

• [RISCV] Update two RISCV codegen tests after rL323991

  Show description for 4cc68b7
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  4cc68b7

Commits on Jan 18, 2018

• [RISCV] Codegen support for the standard RV32M instruction set extension

  Show description for eac9f87
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  eac9f87

• [RISCV] Implement frame pointer elimination

  Show description for ff5fe57
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  committed
  ff5fe57

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